Digital calibration technique using a signed counter for charge pump mismatch in phase-locked loops
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Jeong, Chan-Hui | - |
dc.contributor.author | Kim, Kyu-Young | - |
dc.contributor.author | Kwon, Chan-Keun | - |
dc.contributor.author | Kim, Hoonki | - |
dc.contributor.author | Kim, Soo-Won | - |
dc.date.accessioned | 2021-09-05T19:40:32Z | - |
dc.date.available | 2021-09-05T19:40:32Z | - |
dc.date.created | 2021-06-15 | - |
dc.date.issued | 2013-11 | - |
dc.identifier.issn | 1751-858X | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/101739 | - |
dc.description.abstract | The authors adopt a digital technique to calibrate the current mismatch of the charge pump in phase-locked loops. The proposed digital calibration technique using a signed counter reduces the calibration time up to a minimum of 64% as compared with the other techniques. This technique is designed by a standard 0.18 m CMOS technology. The calibration time is 32.8 s, the average power is 6.2 mW at a 1.8 V power supply and the effective area is 0.263 mm(2). | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | INST ENGINEERING TECHNOLOGY-IET | - |
dc.subject | SPUR REDUCTION | - |
dc.subject | GLITCH | - |
dc.title | Digital calibration technique using a signed counter for charge pump mismatch in phase-locked loops | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Soo-Won | - |
dc.identifier.doi | 10.1049/iet-cds.2013.0011 | - |
dc.identifier.scopusid | 2-s2.0-84890882621 | - |
dc.identifier.wosid | 000328730900002 | - |
dc.identifier.bibliographicCitation | IET CIRCUITS DEVICES & SYSTEMS, v.7, no.6, pp.313 - 318 | - |
dc.relation.isPartOf | IET CIRCUITS DEVICES & SYSTEMS | - |
dc.citation.title | IET CIRCUITS DEVICES & SYSTEMS | - |
dc.citation.volume | 7 | - |
dc.citation.number | 6 | - |
dc.citation.startPage | 313 | - |
dc.citation.endPage | 318 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | SPUR REDUCTION | - |
dc.subject.keywordPlus | GLITCH | - |
dc.subject.keywordAuthor | calibration | - |
dc.subject.keywordAuthor | CMOS digital integrated circuits | - |
dc.subject.keywordAuthor | digital phase locked loops | - |
dc.subject.keywordAuthor | charge pump circuits | - |
dc.subject.keywordAuthor | digital calibration technique | - |
dc.subject.keywordAuthor | signed counter | - |
dc.subject.keywordAuthor | charge pump mismatch | - |
dc.subject.keywordAuthor | phase-locked loops | - |
dc.subject.keywordAuthor | standard CMOS technology | - |
dc.subject.keywordAuthor | size 0 | - |
dc.subject.keywordAuthor | 18 mum | - |
dc.subject.keywordAuthor | time 32 | - |
dc.subject.keywordAuthor | 8 mus | - |
dc.subject.keywordAuthor | power 6 | - |
dc.subject.keywordAuthor | 2 mW | - |
dc.subject.keywordAuthor | voltage 1 | - |
dc.subject.keywordAuthor | 8 V | - |
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