Performance evaluation of many-core systems: case study with TILEPro64
DC Field | Value | Language |
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dc.contributor.author | Kim, Han-Yee | - |
dc.contributor.author | Kim, Young-Hwan | - |
dc.contributor.author | Yu, HeonChang | - |
dc.contributor.author | Suh, Taeweon | - |
dc.date.accessioned | 2021-09-06T00:06:03Z | - |
dc.date.available | 2021-09-06T00:06:03Z | - |
dc.date.created | 2021-06-14 | - |
dc.date.issued | 2013-07 | - |
dc.identifier.issn | 1751-8601 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/102790 | - |
dc.description.abstract | This study evaluates the performance of the 64-core-based TILEPro64, and compares it with Core i7 and Atom by executing three benchmark programs: a synthetic bench, SPEC CINT2006 and SPLASH-2. TILEPro64 is not advertised for regular applications such as SPLASH-2. However, its internal many-core structure makes it worth investigating the performance characteristic with conventional benchmarks. The synthetic benchmark shows that the stall time because of on-chip network takes up to 85% of total execution time in TILEPro64. The single-core performance with CINT2006 reports that Core i7 and Atom deliver 15.4 x and 3.8 x superior performance to TILEPro64, respectively. The parallel performance with SPLASH-2 reports a similar trend. Comparing the fastest execution times, Core i7 boasts of a 19.2 x faster performance than TILEPro64 and even Atom outperforms TILEPro64 by 2.6 x on average. It came as a surprise that even Atom outperforms TILEPro64 in most of the benchmark programs. The highest number of last-level cache misses is a major culprit for low performance. The forerunner many-core products such as TILEPro64 offer excellent test-beds for polishing, adjusting and reshaping many-core architecture in the right direction. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | INST ENGINEERING TECHNOLOGY-IET | - |
dc.title | Performance evaluation of many-core systems: case study with TILEPro64 | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Yu, HeonChang | - |
dc.contributor.affiliatedAuthor | Suh, Taeweon | - |
dc.identifier.doi | 10.1049/iet-cdt.2012.0101 | - |
dc.identifier.scopusid | 2-s2.0-84880686868 | - |
dc.identifier.wosid | 000321712100001 | - |
dc.identifier.bibliographicCitation | IET COMPUTERS AND DIGITAL TECHNIQUES, v.7, no.4, pp.143 - 154 | - |
dc.relation.isPartOf | IET COMPUTERS AND DIGITAL TECHNIQUES | - |
dc.citation.title | IET COMPUTERS AND DIGITAL TECHNIQUES | - |
dc.citation.volume | 7 | - |
dc.citation.number | 4 | - |
dc.citation.startPage | 143 | - |
dc.citation.endPage | 154 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Theory & Methods | - |
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