A 1.62 Gb/s-2.7 Gb/s Referenceless Transceiver for DisplayPort v1.1a With Weighted Phase and Frequency Detection
DC Field | Value | Language |
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dc.contributor.author | Song, Junyoung | - |
dc.contributor.author | Jung, Inhwa | - |
dc.contributor.author | Song, Minyoung | - |
dc.contributor.author | Kwak, Young-Ho | - |
dc.contributor.author | Hwang, Sewook | - |
dc.contributor.author | Kim, Chulwoo | - |
dc.date.accessioned | 2021-09-06T04:38:11Z | - |
dc.date.available | 2021-09-06T04:38:11Z | - |
dc.date.created | 2021-06-14 | - |
dc.date.issued | 2013-02 | - |
dc.identifier.issn | 1549-8328 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/104029 | - |
dc.description.abstract | This paper proposes a 2.7 Gb/s referenceless transceiver with weighted PFD for frequency detection of random signals. A single loop referenceless CDR is also proposed to overcome the disadvantages of a dual loop CDR. The ANSI 8b/10b encoder & decoder with the scrambler, the serializer & de-serializer, and the output driver with pre-emphasis are included in the proposed transceiver architecture for DisplayPort v1.1a. The jitter of the generated clock at the Tx PLL is 3.28 ps(rms) at 2.7 Gb/s with 1.2 V supply. The eye opening of the transmitter output with 3 m cable is 0.54 UI. The measured jitter of the recovered clock at the CDR is 1.57 ps(rms), and BER is less than 10(-12). The receiver consumes 23 mW at 2.7 Gb/s with 1.2 V supply. The CDR core and transceiver occupy 0.07 mm(2) and 0.94 mm(2), respectively, in a 0.13 mu m 1P8M CMOS process. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | DATA RECOVERY CIRCUIT | - |
dc.subject | CMOS CLOCK | - |
dc.subject | INTERFACE | - |
dc.title | A 1.62 Gb/s-2.7 Gb/s Referenceless Transceiver for DisplayPort v1.1a With Weighted Phase and Frequency Detection | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Chulwoo | - |
dc.identifier.doi | 10.1109/TCSI.2012.2215779 | - |
dc.identifier.scopusid | 2-s2.0-84873414005 | - |
dc.identifier.wosid | 000314267000002 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.60, no.2, pp.268 - 278 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | - |
dc.citation.title | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | - |
dc.citation.volume | 60 | - |
dc.citation.number | 2 | - |
dc.citation.startPage | 268 | - |
dc.citation.endPage | 278 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | DATA RECOVERY CIRCUIT | - |
dc.subject.keywordPlus | CMOS CLOCK | - |
dc.subject.keywordPlus | INTERFACE | - |
dc.subject.keywordAuthor | Clock and data recovery | - |
dc.subject.keywordAuthor | phase and frequency detection | - |
dc.subject.keywordAuthor | phase detection | - |
dc.subject.keywordAuthor | referenceless transceiver | - |
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