A 20 Gb/s Clock and Data Recovery With a Ping-Pong Delay Line for Unlimited Phase Shifting in 65 nm CMOS Process
- Authors
- Kwak, Young-Ho; Kim, Yongtae; Hwang, Sewook; Kim, Chulwoo
- Issue Date
- 2월-2013
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- CDR; DLL; infinite phase shift; oversampling; ping-pong delay line; PLL; receiver; voltage regulator; wide tracking range; 65 nm CMOS process
- Citation
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.60, no.2, pp.303 - 313
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
- Volume
- 60
- Number
- 2
- Start Page
- 303
- End Page
- 313
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/104145
- DOI
- 10.1109/TCSI.2012.2215781
- ISSN
- 1549-8328
- Abstract
- This paper describes a 20 Gb/s receiver with a DLL-based CDR, which uses a proposed Ping-Pong delay line (PPDL) in order to ameliorate the limited operating range problem of the DLL. The unlimited phase shifting algorithm with the PPDL extends the tracking range of the DLL-based CDR. The PPDL correlates two variable delay lines and swaps each other whenever one of them reaches its operational limit. The chip occupies 0.24 mm(2) in 65 nm CMOS process. The power efficiency of the data transfer is 8.46 mW/Gb/s. The measured jitter of the 5 GHz clock is 1.125 ps(rms) and the data eye opening is 0.613UI.
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Collections - College of Engineering > School of Electrical Engineering > 1. Journal Articles
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