New Bit Parallel Multiplier With Low Space Complexity for All Irreducible Trinomials Over GF(2(n))
DC Field | Value | Language |
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dc.contributor.author | Cho, Young In | - |
dc.contributor.author | Chang, Nam Su | - |
dc.contributor.author | Kim, Chang Han | - |
dc.contributor.author | Park, Young-Ho | - |
dc.contributor.author | Hong, Seokhie | - |
dc.date.accessioned | 2021-09-06T15:01:48Z | - |
dc.date.available | 2021-09-06T15:01:48Z | - |
dc.date.created | 2021-06-15 | - |
dc.date.issued | 2012-10 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/107346 | - |
dc.description.abstract | Koc and Sunar proposed an architecture of the Mastrovito multiplier for the irreducible trinomial f(x) = x(n) + x(k) + 1, where k not equal n/2 to reduce the time complexity. Also, many multipliers based on the Karatsuba-Ofman algorithm (KOA) was proposed that sacrificed time efficiency for low space complexity. In this paper, a new multiplication formula which is a variant of KOA presented. We also provide a straightforward architecture of a non-pipelined bit-parallel multiplier using the new formula. The proposed multiplier has lower space complexity than and comparable time complexity to previous Mastrovito multipliers' for all irreducible trinomials. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | FINITE-FIELD MULTIPLIERS | - |
dc.subject | MASTROVITO MULTIPLIER | - |
dc.subject | POLYNOMIAL BASIS | - |
dc.subject | GF(2(M)) | - |
dc.subject | ARCHITECTURE | - |
dc.subject | DESIGN | - |
dc.title | New Bit Parallel Multiplier With Low Space Complexity for All Irreducible Trinomials Over GF(2(n)) | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Hong, Seokhie | - |
dc.identifier.doi | 10.1109/TVLSI.2011.2162594 | - |
dc.identifier.scopusid | 2-s2.0-84864777872 | - |
dc.identifier.wosid | 000306922400018 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.20, no.10, pp.1903 - 1908 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.title | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.volume | 20 | - |
dc.citation.number | 10 | - |
dc.citation.startPage | 1903 | - |
dc.citation.endPage | 1908 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | FINITE-FIELD MULTIPLIERS | - |
dc.subject.keywordPlus | MASTROVITO MULTIPLIER | - |
dc.subject.keywordPlus | POLYNOMIAL BASIS | - |
dc.subject.keywordPlus | GF(2(M)) | - |
dc.subject.keywordPlus | ARCHITECTURE | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordAuthor | Bit-parallel multiplier | - |
dc.subject.keywordAuthor | finite field | - |
dc.subject.keywordAuthor | irreducible trinomial | - |
dc.subject.keywordAuthor | Mastrovito multiplication | - |
dc.subject.keywordAuthor | polynomial basis | - |
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