250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 mu m CMOS
DC Field | Value | Language |
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dc.contributor.author | Lee, Sang-Yoon | - |
dc.contributor.author | Lee, Hyung-Rok | - |
dc.contributor.author | Kwak, Young-Ho | - |
dc.contributor.author | Choi, Woo-Seok | - |
dc.contributor.author | Yoo, Byoung-Joo | - |
dc.contributor.author | Shim, Daeyun | - |
dc.contributor.author | Kim, Chulwoo | - |
dc.contributor.author | Jeong, Deog-Kyoon | - |
dc.date.accessioned | 2021-09-07T06:47:09Z | - |
dc.date.available | 2021-09-07T06:47:09Z | - |
dc.date.created | 2021-06-18 | - |
dc.date.issued | 2011-11 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/111297 | - |
dc.description.abstract | A multi-port serial link with wide-range CDR using digital vernier phase shifting and dual-mode control is presented. The proposed vernier phase shifter generates finely-spaced phase steps and provides unlimited phase rotating with a 13.34-ps phase step at 5 Gbps. By inherently digital nature, the vernier phase shifter enables semi-digital dual-loop CDR with precise tracking performance, and with the dual-mode control, the proposed CDR extends the operating range from 250 Mbps to 5 Gbps and achieves a BER of less than 10(-12) at 5 Gbps with 2(9)-1 PRBS. Fabricated in a 0.13-mu m CMOS process, the main PLL and the single receiver dissipate 9.0 mW and 19.2 mW respectively at 5 Gbps from a 1.2 V supply. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | DELAY-LOCKED LOOP | - |
dc.subject | CLOCK | - |
dc.subject | OPERATION | - |
dc.subject | INTERFACE | - |
dc.subject | PLL | - |
dc.subject | DLL | - |
dc.title | 250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 mu m CMOS | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Chulwoo | - |
dc.identifier.doi | 10.1109/JSSC.2011.2164032 | - |
dc.identifier.wosid | 000296234100013 | - |
dc.identifier.bibliographicCitation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.46, no.11, pp.2560 - 2570 | - |
dc.relation.isPartOf | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.citation.title | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.citation.volume | 46 | - |
dc.citation.number | 11 | - |
dc.citation.startPage | 2560 | - |
dc.citation.endPage | 2570 | - |
dc.type.rims | ART | - |
dc.type.docType | Article; Proceedings Paper | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | DELAY-LOCKED LOOP | - |
dc.subject.keywordPlus | CLOCK | - |
dc.subject.keywordPlus | OPERATION | - |
dc.subject.keywordPlus | INTERFACE | - |
dc.subject.keywordPlus | PLL | - |
dc.subject.keywordPlus | DLL | - |
dc.subject.keywordAuthor | Clock and data recovery | - |
dc.subject.keywordAuthor | semi-digital dual-loop | - |
dc.subject.keywordAuthor | vernier phase shifter | - |
dc.subject.keywordAuthor | wide-range CDR | - |
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