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250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 mu m CMOS

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dc.contributor.authorLee, Sang-Yoon-
dc.contributor.authorLee, Hyung-Rok-
dc.contributor.authorKwak, Young-Ho-
dc.contributor.authorChoi, Woo-Seok-
dc.contributor.authorYoo, Byoung-Joo-
dc.contributor.authorShim, Daeyun-
dc.contributor.authorKim, Chulwoo-
dc.contributor.authorJeong, Deog-Kyoon-
dc.date.accessioned2021-09-07T06:47:09Z-
dc.date.available2021-09-07T06:47:09Z-
dc.date.created2021-06-18-
dc.date.issued2011-11-
dc.identifier.issn0018-9200-
dc.identifier.urihttps://scholar.korea.ac.kr/handle/2021.sw.korea/111297-
dc.description.abstractA multi-port serial link with wide-range CDR using digital vernier phase shifting and dual-mode control is presented. The proposed vernier phase shifter generates finely-spaced phase steps and provides unlimited phase rotating with a 13.34-ps phase step at 5 Gbps. By inherently digital nature, the vernier phase shifter enables semi-digital dual-loop CDR with precise tracking performance, and with the dual-mode control, the proposed CDR extends the operating range from 250 Mbps to 5 Gbps and achieves a BER of less than 10(-12) at 5 Gbps with 2(9)-1 PRBS. Fabricated in a 0.13-mu m CMOS process, the main PLL and the single receiver dissipate 9.0 mW and 19.2 mW respectively at 5 Gbps from a 1.2 V supply.-
dc.languageEnglish-
dc.language.isoen-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectDELAY-LOCKED LOOP-
dc.subjectCLOCK-
dc.subjectOPERATION-
dc.subjectINTERFACE-
dc.subjectPLL-
dc.subjectDLL-
dc.title250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 mu m CMOS-
dc.typeArticle-
dc.contributor.affiliatedAuthorKim, Chulwoo-
dc.identifier.doi10.1109/JSSC.2011.2164032-
dc.identifier.wosid000296234100013-
dc.identifier.bibliographicCitationIEEE JOURNAL OF SOLID-STATE CIRCUITS, v.46, no.11, pp.2560 - 2570-
dc.relation.isPartOfIEEE JOURNAL OF SOLID-STATE CIRCUITS-
dc.citation.titleIEEE JOURNAL OF SOLID-STATE CIRCUITS-
dc.citation.volume46-
dc.citation.number11-
dc.citation.startPage2560-
dc.citation.endPage2570-
dc.type.rimsART-
dc.type.docTypeArticle; Proceedings Paper-
dc.description.journalClass1-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordPlusDELAY-LOCKED LOOP-
dc.subject.keywordPlusCLOCK-
dc.subject.keywordPlusOPERATION-
dc.subject.keywordPlusINTERFACE-
dc.subject.keywordPlusPLL-
dc.subject.keywordPlusDLL-
dc.subject.keywordAuthorClock and data recovery-
dc.subject.keywordAuthorsemi-digital dual-loop-
dc.subject.keywordAuthorvernier phase shifter-
dc.subject.keywordAuthorwide-range CDR-
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