A 140 Mb/s to 1.96 Gb/s Referenceless Transceiver With 7.2 mu s Frequency Acquisition Time
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Jung, Inhwa | - |
dc.contributor.author | Shin, Daejung | - |
dc.contributor.author | Kim, Taejin | - |
dc.contributor.author | Kim, Chulwoo | - |
dc.date.accessioned | 2021-09-07T11:01:53Z | - |
dc.date.available | 2021-09-07T11:01:53Z | - |
dc.date.created | 2021-06-14 | - |
dc.date.issued | 2011-07 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/112092 | - |
dc.description.abstract | This paper presents a design of a wide-range transceiver without an external reference clock. The self-biased and multi-band PLL with self-initialization technique is used for the wide-operating range of 140 Mb/s to 1.96 Gb/s and fast frequency acquisition time of 7.2 mu s. A linear phase detector which has no dead-zone problem is proposed for a phase adjustment with a low-jitter performance. The rms jitter of the recovered clock is 11.4 ps at 70 MHz operation. The overall transceiver consumes 388 mW at 2.5 V supply and occupies 3.41 mm(2) in a 0.25-mu m 1P5M CMOS technology. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A 140 Mb/s to 1.96 Gb/s Referenceless Transceiver With 7.2 mu s Frequency Acquisition Time | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Chulwoo | - |
dc.identifier.doi | 10.1109/TVLSI.2010.2047953 | - |
dc.identifier.scopusid | 2-s2.0-79959699201 | - |
dc.identifier.wosid | 000292098600017 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.19, no.7, pp.1310 - 1315 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.title | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.volume | 19 | - |
dc.citation.number | 7 | - |
dc.citation.startPage | 1310 | - |
dc.citation.endPage | 1315 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordAuthor | Clock and data recovery (CDR) | - |
dc.subject.keywordAuthor | embedded clock | - |
dc.subject.keywordAuthor | linear PD | - |
dc.subject.keywordAuthor | low-jitter | - |
dc.subject.keywordAuthor | low voltage differential signaling (LVDS) | - |
dc.subject.keywordAuthor | transceiver | - |
dc.subject.keywordAuthor | wide-range | - |
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