Latch-based FPGA emulation method for design verification: case study with microprocessor

Abstract

Using latches in a digital design is considered wrong owing to the timing issue. Field-programmable gate array (FPGA) vendors also recommend flip-flops instead of latches in emulation. In this reported work, however, the usefulness and benefit of utilising latches in FPGA emulation for processor design verification is demonstrated. The study shows that a latch-based register file provides the seamless capability of functionality validation, whereas the flip-flop based one requires modification to the original design, potentially harming the completeness of functional verification. Experiment results with Xilinx and Altera devices show marginal differences in terms of emulation performance and area requirement in both approaches. This study reveals that replacing SRAM with latches rather than flip-flops is appealing and preferable in emulation with FPGAs.