카운터 기반 디지털 보상 기법을 이용한 위상 고정 루프
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 정찬희 | - |
dc.contributor.author | Ammar Abdullah | - |
dc.contributor.author | 이관주 | - |
dc.contributor.author | 김훈기 | - |
dc.contributor.author | 김수원 | - |
dc.date.accessioned | 2021-09-07T19:58:22Z | - |
dc.date.available | 2021-09-07T19:58:22Z | - |
dc.date.created | 2021-06-17 | - |
dc.date.issued | 2011 | - |
dc.identifier.issn | 1975-8359 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/114470 | - |
dc.description.abstract | A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in phase-locked loops. A 2 GHz charge pump PLL (CPPLL) is used to justify the proposed calibration technique. The proposed digital calibration technique is implemented simply using a counter. The proposed calibration technique reduces the calibration time by up to a maximum of 50% compared other with techniques. Also by using a dual-mode CP, good current matching characteristics can be achieved to compensate 0.5μA current mismatch in CP. It was designed in a standard 0.13μm CMOS technology. The maximum calibration time is 33.6μs and the average power is 18.38mW with 1.5V power supply and effective area is 0.1804mm2. | - |
dc.language | Korean | - |
dc.language.iso | ko | - |
dc.publisher | 대한전기학회 | - |
dc.title | 카운터 기반 디지털 보상 기법을 이용한 위상 고정 루프 | - |
dc.title.alternative | Phase-Locked Loops using Digital Calibration Technique with counter | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | 김수원 | - |
dc.identifier.bibliographicCitation | 전기학회논문지, v.60, no.2, pp.320 - 324 | - |
dc.relation.isPartOf | 전기학회논문지 | - |
dc.citation.title | 전기학회논문지 | - |
dc.citation.volume | 60 | - |
dc.citation.number | 2 | - |
dc.citation.startPage | 320 | - |
dc.citation.endPage | 324 | - |
dc.type.rims | ART | - |
dc.identifier.kciid | ART001523537 | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scopus | - |
dc.description.journalRegisteredClass | kci | - |
dc.subject.keywordAuthor | Charge pump(CP) mismatch | - |
dc.subject.keywordAuthor | Digital calibration | - |
dc.subject.keywordAuthor | Charge pump phase-locked loop(CPPLL) | - |
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