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Compact Modeling for Circuit Simulation Considering TID Effect in 65nm CMOS Technology

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dc.contributor.authorLee, Hyung-Min-
dc.date.accessioned2021-08-27T16:02:52Z-
dc.date.available2021-08-27T16:02:52Z-
dc.date.created2021-04-22-
dc.date.issued2019-07-01-
dc.identifier.urihttps://scholar.korea.ac.kr/handle/2021.sw.korea/11526-
dc.publisherIEIE & IEICE-ES-
dc.titleCompact Modeling for Circuit Simulation Considering TID Effect in 65nm CMOS Technology-
dc.title.alternativeCompact Modeling for Circuit Simulation Considering TID Effect in 65nm CMOS Technology-
dc.typeConference-
dc.contributor.affiliatedAuthorLee, Hyung-Min-
dc.identifier.bibliographicCitationAsia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices-
dc.relation.isPartOfAsia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices-
dc.relation.isPartOfAWAD Proceeding-
dc.citation.titleAsia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices-
dc.citation.conferencePlaceKO-
dc.citation.conferenceDate2019-07-01-
dc.type.rimsCONF-
dc.description.journalClass1-
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