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Compact Modeling for Circuit Simulation Considering TID Effect in 65nm CMOS Technology
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Lee, Hyung-Min | - |
| dc.date.accessioned | 2021-08-27T16:02:52Z | - |
| dc.date.available | 2021-08-27T16:02:52Z | - |
| dc.date.created | 2021-04-22 | - |
| dc.date.issued | 2019-07-01 | - |
| dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/11526 | - |
| dc.publisher | IEIE & IEICE-ES | - |
| dc.title | Compact Modeling for Circuit Simulation Considering TID Effect in 65nm CMOS Technology | - |
| dc.title.alternative | Compact Modeling for Circuit Simulation Considering TID Effect in 65nm CMOS Technology | - |
| dc.type | Conference | - |
| dc.contributor.affiliatedAuthor | Lee, Hyung-Min | - |
| dc.identifier.bibliographicCitation | Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices | - |
| dc.relation.isPartOf | Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices | - |
| dc.relation.isPartOf | AWAD Proceeding | - |
| dc.citation.title | Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices | - |
| dc.citation.conferencePlace | KO | - |
| dc.citation.conferenceDate | 2019-07-01 | - |
| dc.type.rims | CONF | - |
| dc.description.journalClass | 1 | - |
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