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Load Unbalancing Strategy for Multicore Embedded Processors

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dc.contributor.authorJeon, Hyeran-
dc.contributor.authorLee, Woo Hyong-
dc.contributor.authorChung, Sung Woo-
dc.date.accessioned2021-09-07T23:50:46Z-
dc.date.available2021-09-07T23:50:46Z-
dc.date.issued2010-10-
dc.identifier.issn0018-9340-
dc.identifier.issn1557-9956-
dc.identifier.urihttps://scholar.korea.ac.kr/handle/2021.sw.korea/115579-
dc.description.abstractLoad balancing has been known as an essential feature for enhancing the performance of distributed systems. For embedded systems, however, this is not always true since load balancing leads to lavish power consumption by fully utilizing all the embedded cores even for a small number of tasks. Furthermore, the previously proposed load unbalancing strategies do not concern much about the characteristics of the embedded system's real workload. In this paper, to resolve this problem, we propose a novel load unbalancing strategy based on the task characteristics: periodic and aperiodic. In the proposed strategy, the periodic tasks that are more likely to be executed repeatedly are concentrated on the minimum number of cores, whereas the aperiodic tasks that are not likely to occur again soon are distributed to the maximum number of cores. The experimental results on an ARM11MPCore test chip show that the proposed strategy reduces power consumption and mean waiting time of the aperiodic tasks by up to 26 percent and 82 percent, respectively, compared to the load balancing strategy. As compared to the aggressive load unbalancing strategy, the proposed strategy also reduces mean waiting time of the aperiodic tasks by 92 percent with similar power efficiency.-
dc.format.extent7-
dc.language영어-
dc.language.isoENG-
dc.publisherIEEE COMPUTER SOC-
dc.titleLoad Unbalancing Strategy for Multicore Embedded Processors-
dc.typeArticle-
dc.publisher.location미국-
dc.identifier.doi10.1109/TC.2009.181-
dc.identifier.scopusid2-s2.0-77956247909-
dc.identifier.wosid000282239300011-
dc.identifier.bibliographicCitationIEEE TRANSACTIONS ON COMPUTERS, v.59, no.10, pp 1434 - 1440-
dc.citation.titleIEEE TRANSACTIONS ON COMPUTERS-
dc.citation.volume59-
dc.citation.number10-
dc.citation.startPage1434-
dc.citation.endPage1440-
dc.type.docTypeArticle-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClasssci-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaComputer Science-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryComputer Science, Hardware & Architecture-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordPlusSYSTEM-
dc.subject.keywordAuthorDistributed architectures-
dc.subject.keywordAuthorload balancing-
dc.subject.keywordAuthortask assignment-
dc.subject.keywordAuthorreal-time systems-
dc.subject.keywordAuthorembedded systems-
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