A new bit-serial multiplier over GF(p(m)) using irreducible trinomials
DC Field | Value | Language |
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dc.contributor.author | Chang, Nam Su | - |
dc.contributor.author | Kim, Tae Hyun | - |
dc.contributor.author | Kim, Chang Han | - |
dc.contributor.author | Han, Dong-Guk | - |
dc.contributor.author | Lim, Jongin | - |
dc.date.accessioned | 2021-09-08T01:41:56Z | - |
dc.date.available | 2021-09-08T01:41:56Z | - |
dc.date.created | 2021-06-11 | - |
dc.date.issued | 2010-07 | - |
dc.identifier.issn | 0898-1221 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/116114 | - |
dc.description.abstract | Pairing-based schemes, such as identity-based cryptosystem, are widely used for future computing environments. Hence the work of hardware architectures for GF(p(m)) has been brought to public attention for the past few years since most of the pairing-based schemes are implemented using arithmetic operations over GF(p(m)) defined by irreducible trinomials. This paper proposes a new most significant elements (MSE)-first serial multiplier for GF(p(m)), where p > 2, which is more efficient than least significant elements (LSE)-first multipliers from the point of view of both the time delay and the size of registers. In particular, the proposed multiplier has an advantage when the extension degree of finite fields m is large and the characteristic of finite fields p is small like GF(3(m)), GF(5(m)), and GF(7(m)) used in pairing-based cryptosystems. (C) 2010 Elsevier Ltd. All rights reserved. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | PERGAMON-ELSEVIER SCIENCE LTD | - |
dc.subject | ARCHITECTURES | - |
dc.subject | HARDWARE | - |
dc.subject | FIELDS | - |
dc.subject | FPGA | - |
dc.title | A new bit-serial multiplier over GF(p(m)) using irreducible trinomials | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Lim, Jongin | - |
dc.identifier.doi | 10.1016/j.camwa.2009.12.034 | - |
dc.identifier.scopusid | 2-s2.0-77955713994 | - |
dc.identifier.wosid | 000279485900021 | - |
dc.identifier.bibliographicCitation | COMPUTERS & MATHEMATICS WITH APPLICATIONS, v.60, no.2, pp.355 - 361 | - |
dc.relation.isPartOf | COMPUTERS & MATHEMATICS WITH APPLICATIONS | - |
dc.citation.title | COMPUTERS & MATHEMATICS WITH APPLICATIONS | - |
dc.citation.volume | 60 | - |
dc.citation.number | 2 | - |
dc.citation.startPage | 355 | - |
dc.citation.endPage | 361 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Mathematics | - |
dc.relation.journalWebOfScienceCategory | Mathematics, Applied | - |
dc.subject.keywordPlus | ARCHITECTURES | - |
dc.subject.keywordPlus | HARDWARE | - |
dc.subject.keywordPlus | FIELDS | - |
dc.subject.keywordPlus | FPGA | - |
dc.subject.keywordAuthor | Finite field | - |
dc.subject.keywordAuthor | Irreducible trinomial | - |
dc.subject.keywordAuthor | Bit-serial multiplier | - |
dc.subject.keywordAuthor | Pairing-based cryptography | - |
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