An Antiharmonic, Programmable, DLL-Based Frequency Multiplier for Dynamic Frequency Scaling
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Ok, Sunghwa | - |
dc.contributor.author | Chung, Kyunghoon | - |
dc.contributor.author | Koo, Jabeom | - |
dc.contributor.author | Kim, Chulwoo | - |
dc.date.accessioned | 2021-09-08T01:48:16Z | - |
dc.date.available | 2021-09-08T01:48:16Z | - |
dc.date.created | 2021-06-11 | - |
dc.date.issued | 2010-07 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/116148 | - |
dc.description.abstract | This paper describes a new delay-locked loop (DLL)-based frequency multiplier, which includes a lock controller and a phase detector to solve the false lock problem and overcome the limited locking range of conventional DLLs. By using the multiple clock phases of the DLL, the lock controller is able to indicate whether the delay time of the VCDL is within the correct locking range or not. A differentially controlled edge combiner is also proposed for the frequency multiplication. The antiharmonic DLL-based frequency multiplier, implemented in a 0.18-mu m CMOS process, occupies an active area of 0.043 mm(2), and dissipates 36.7 mW at 1.7 GHz. The measured root mean square jitter and peak-to-peak jitter for the multiplied output clock at 1.7 GHz are 2.64 and 16.8 ps, respectively. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | DELAY-LOCKED LOOP | - |
dc.subject | ADAPTIVE BANDWIDTH CONTROL | - |
dc.subject | CLOCK GENERATOR | - |
dc.subject | RANGE | - |
dc.subject | SYNTHESIZER | - |
dc.subject | OSCILLATOR | - |
dc.subject | NOISE | - |
dc.subject | CYCLE | - |
dc.subject | PLL | - |
dc.title | An Antiharmonic, Programmable, DLL-Based Frequency Multiplier for Dynamic Frequency Scaling | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Chulwoo | - |
dc.identifier.doi | 10.1109/TVLSI.2009.2019757 | - |
dc.identifier.scopusid | 2-s2.0-77954083773 | - |
dc.identifier.wosid | 000278996600010 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.18, no.7, pp.1130 - 1134 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.title | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.volume | 18 | - |
dc.citation.number | 7 | - |
dc.citation.startPage | 1130 | - |
dc.citation.endPage | 1134 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | DELAY-LOCKED LOOP | - |
dc.subject.keywordPlus | ADAPTIVE BANDWIDTH CONTROL | - |
dc.subject.keywordPlus | CLOCK GENERATOR | - |
dc.subject.keywordPlus | RANGE | - |
dc.subject.keywordPlus | SYNTHESIZER | - |
dc.subject.keywordPlus | OSCILLATOR | - |
dc.subject.keywordPlus | NOISE | - |
dc.subject.keywordPlus | CYCLE | - |
dc.subject.keywordPlus | PLL | - |
dc.subject.keywordAuthor | Antiharmonic lock | - |
dc.subject.keywordAuthor | delay-locked loop (DLL) | - |
dc.subject.keywordAuthor | false lock | - |
dc.subject.keywordAuthor | frequency multiplication | - |
dc.subject.keywordAuthor | limited locking range | - |
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