Synthesis of Small Diameter Silicon Nanowires on SiO2 and Si3N4 Surfaces
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Ahn, Jae Hyun | - |
dc.contributor.author | Lee, Jae-Hyun | - |
dc.contributor.author | Koo, Tae-Woong | - |
dc.contributor.author | Kang, MyungGil | - |
dc.contributor.author | Whang, Dongmok | - |
dc.contributor.author | Hwang, SungWoo | - |
dc.date.accessioned | 2021-09-08T03:23:35Z | - |
dc.date.available | 2021-09-08T03:23:35Z | - |
dc.date.created | 2021-06-11 | - |
dc.date.issued | 2010-05 | - |
dc.identifier.issn | 0916-8524 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/116498 | - |
dc.description.abstract | We report successful bottom-up synthesis of small diameter silicon nanowires (SiNWs) on SiO2 and Si3N4 surfaces. SiNWs with diameter comparable to the diameter of the Au nano-particles (10-20 nm) were grown on these surfaces, as well as on Si substrates which are commonly used for the nanowire growth. The growth temperature for obtaining a high density of SiNWs on SiO2 and Si3N4 substrates is higher (460-470 degrees C) than that of the case of normal Si substrates (440 degrees C). The growth on patterned substrates demonstrates that SiNWs can be selectively grown. Furthermore, the guided growth over metal structures is also shown to be possible. Selective growth of SiNWs on pre-patterned surfaces opens up the possibility of self-aligning SiNWs for the integration of complex device structures. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG | - |
dc.subject | PERFORMANCE | - |
dc.subject | GROWTH | - |
dc.subject | ARRAYS | - |
dc.subject | ELECTRONICS | - |
dc.subject | TRANSISTORS | - |
dc.title | Synthesis of Small Diameter Silicon Nanowires on SiO2 and Si3N4 Surfaces | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Hwang, SungWoo | - |
dc.identifier.doi | 10.1587/transele.E93.C.546 | - |
dc.identifier.scopusid | 2-s2.0-77951778071 | - |
dc.identifier.wosid | 000281341500004 | - |
dc.identifier.bibliographicCitation | IEICE TRANSACTIONS ON ELECTRONICS, v.E93C, no.5, pp.546 - 551 | - |
dc.relation.isPartOf | IEICE TRANSACTIONS ON ELECTRONICS | - |
dc.citation.title | IEICE TRANSACTIONS ON ELECTRONICS | - |
dc.citation.volume | E93C | - |
dc.citation.number | 5 | - |
dc.citation.startPage | 546 | - |
dc.citation.endPage | 551 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | PERFORMANCE | - |
dc.subject.keywordPlus | GROWTH | - |
dc.subject.keywordPlus | ARRAYS | - |
dc.subject.keywordPlus | ELECTRONICS | - |
dc.subject.keywordPlus | TRANSISTORS | - |
dc.subject.keywordAuthor | silicon nanowire | - |
dc.subject.keywordAuthor | VLS | - |
dc.subject.keywordAuthor | bottom-up synthesis | - |
dc.subject.keywordAuthor | selective growth | - |
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