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VERIFICATION OF PLC PROGRAMS WRITTEN IN FBD WITH VIS
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Yoo, Junbeom | - |
| dc.contributor.author | Cha, Sungdeok | - |
| dc.contributor.author | Jee, Eunkyoung | - |
| dc.date.accessioned | 2021-09-08T20:07:57Z | - |
| dc.date.available | 2021-09-08T20:07:57Z | - |
| dc.date.created | 2021-06-19 | - |
| dc.date.issued | 2009-02 | - |
| dc.identifier.issn | 1738-5733 | - |
| dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/120635 | - |
| dc.description.abstract | Verification of programmable logic controller (PLC) programs written in IEC 61131-3 function block diagram (FBD) is essential in the transition from the use of traditional relay-based analog systems to PLC-based digital systems. This paper describes effective use of the well-known verification tool VIS for automatic verification of behavioral equivalences between successive FBD revisions. We formally defined FBD semantics as a state-transition system, developed semantic-preserving translation rules from FBD to Verilog programs, implemented a software tool to support the process, and conducted a case study on a subset of FBDs for APR-1400 reactor protection system design. | - |
| dc.language | English | - |
| dc.language.iso | en | - |
| dc.publisher | KOREAN NUCLEAR SOC | - |
| dc.subject | SPECIFICATION | - |
| dc.subject | SYSTEMS | - |
| dc.subject | DESIGN | - |
| dc.title | VERIFICATION OF PLC PROGRAMS WRITTEN IN FBD WITH VIS | - |
| dc.type | Article | - |
| dc.contributor.affiliatedAuthor | Cha, Sungdeok | - |
| dc.identifier.doi | 10.5516/NET.2009.41.1.079 | - |
| dc.identifier.scopusid | 2-s2.0-62249114181 | - |
| dc.identifier.wosid | 000264223300008 | - |
| dc.identifier.bibliographicCitation | NUCLEAR ENGINEERING AND TECHNOLOGY, v.41, no.1, pp.79 - 90 | - |
| dc.relation.isPartOf | NUCLEAR ENGINEERING AND TECHNOLOGY | - |
| dc.citation.title | NUCLEAR ENGINEERING AND TECHNOLOGY | - |
| dc.citation.volume | 41 | - |
| dc.citation.number | 1 | - |
| dc.citation.startPage | 79 | - |
| dc.citation.endPage | 90 | - |
| dc.type.rims | ART | - |
| dc.type.docType | Article | - |
| dc.identifier.kciid | ART001317574 | - |
| dc.description.journalClass | 1 | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.description.journalRegisteredClass | kci | - |
| dc.relation.journalResearchArea | Nuclear Science & Technology | - |
| dc.relation.journalWebOfScienceCategory | Nuclear Science & Technology | - |
| dc.subject.keywordPlus | SPECIFICATION | - |
| dc.subject.keywordPlus | SYSTEMS | - |
| dc.subject.keywordPlus | DESIGN | - |
| dc.subject.keywordAuthor | Verification | - |
| dc.subject.keywordAuthor | Equivalence Checking | - |
| dc.subject.keywordAuthor | VIS | - |
| dc.subject.keywordAuthor | Verilog | - |
| dc.subject.keywordAuthor | Function Block Diagram | - |
| dc.subject.keywordAuthor | Programmable Logic Controller | - |
| dc.subject.keywordAuthor | IEC-61131 | - |
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