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A pre-emphasis output buffer control scheme for a GDDR3 SDRAM interface

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dc.contributor.authorHwang, Sang Joon-
dc.contributor.authorJun, Young Hyun-
dc.contributor.authorSung, Man Young-
dc.date.accessioned2021-09-09T07:21:27Z-
dc.date.available2021-09-09T07:21:27Z-
dc.date.issued2008-06-25-
dc.identifier.issn1349-2543-
dc.identifier.urihttps://scholar.korea.ac.kr/handle/2021.sw.korea/123358-
dc.description.abstractThe keys to good signal integrity in a Graphic DDR3 (GDDR3) SDRAM interface for a bandwidth up to 1.4 Gbps/pin are the minimization of input/output pin capacitance and the accurate control of the output data skew. The proposed pre-emphasis output buffer control scheme provides output data skew minimization without an increase of input/output pin capacitance. Compared to the conventional scheme, the output data aperture window of proposed scheme has increased by 18% and the data output skew has decreased by 48%.-
dc.format.extent5-
dc.language영어-
dc.language.isoENG-
dc.publisherIEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG-
dc.titleA pre-emphasis output buffer control scheme for a GDDR3 SDRAM interface-
dc.typeArticle-
dc.publisher.location일본-
dc.identifier.doi10.1587/elex.5.446-
dc.identifier.scopusid2-s2.0-47249128625-
dc.identifier.wosid000260186200003-
dc.identifier.bibliographicCitationIEICE ELECTRONICS EXPRESS, v.5, no.12, pp 446 - 450-
dc.citation.titleIEICE ELECTRONICS EXPRESS-
dc.citation.volume5-
dc.citation.number12-
dc.citation.startPage446-
dc.citation.endPage450-
dc.type.docTypeArticle-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordAuthorGDDR3 SDRAM-
dc.subject.keywordAuthortermination-
dc.subject.keywordAuthorsignal integrity-
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