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Surface-Potential-Based Analytical Model of Low-Frequency Noise for Planar-Type Tunnel Field-Effect Transistors

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dc.contributor.authorPark, Yeong-Hun-
dc.contributor.authorYi, Boram-
dc.contributor.authorKim, Seung-Hwan-
dc.contributor.authorShim, Ju-Hyun-
dc.contributor.authorSong, Hyeong-Sub-
dc.contributor.authorSong, Hyun-Dong-
dc.contributor.authorShin, Hyun-Jin-
dc.contributor.authorLee, Hi-Deok-
dc.contributor.authorYang, Ji-Woon-
dc.date.accessioned2021-11-16T19:40:39Z-
dc.date.available2021-11-16T19:40:39Z-
dc.date.created2021-08-30-
dc.date.issued2021-08-
dc.identifier.issn0018-9383-
dc.identifier.urihttps://scholar.korea.ac.kr/handle/2021.sw.korea/127669-
dc.description.abstractAnalytical models of low-frequency noise (LFN) characteristics for planar-type tunnel field-effect-transistors (TFETs) are proposed. A surface-potential-based current-voltage model is developed to physically represent the current fluctuation due to charge trapping/detrapping in the gate dielectric. An LFN model can be analytically derived from the current fluctuation with a reasonable approximation. The proposed model is verified using Technology Computer Aided Design (TCAD) and measurement data, which are in good agreement with each other. The analytical model can not only serve as a valuable reference and tool for low-power analog circuit design but also provide physical insights into the LFN of TFETs.-
dc.languageEnglish-
dc.language.isoen-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectFET-
dc.titleSurface-Potential-Based Analytical Model of Low-Frequency Noise for Planar-Type Tunnel Field-Effect Transistors-
dc.typeArticle-
dc.contributor.affiliatedAuthorYang, Ji-Woon-
dc.identifier.doi10.1109/TED.2021.3087117-
dc.identifier.scopusid2-s2.0-85111642119-
dc.identifier.wosid000678349800055-
dc.identifier.bibliographicCitationIEEE TRANSACTIONS ON ELECTRON DEVICES, v.68, no.8, pp.4051 - 4056-
dc.relation.isPartOfIEEE TRANSACTIONS ON ELECTRON DEVICES-
dc.citation.titleIEEE TRANSACTIONS ON ELECTRON DEVICES-
dc.citation.volume68-
dc.citation.number8-
dc.citation.startPage4051-
dc.citation.endPage4056-
dc.type.rimsART-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalResearchAreaPhysics-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.relation.journalWebOfScienceCategoryPhysics, Applied-
dc.subject.keywordPlusFET-
dc.subject.keywordAuthorTFETs-
dc.subject.keywordAuthorLogic gates-
dc.subject.keywordAuthorSemiconductor device modeling-
dc.subject.keywordAuthorAnalytical models-
dc.subject.keywordAuthorIntegrated circuit modeling-
dc.subject.keywordAuthorComputational modeling-
dc.subject.keywordAuthorTunneling-
dc.subject.keywordAuthorBand-to-band tunneling (BTBT)-
dc.subject.keywordAuthorcompact model-
dc.subject.keywordAuthorflicker noise-
dc.subject.keywordAuthorlow-frequency noise (LFN)-
dc.subject.keywordAuthortunneling FET-
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