Enhancing matrix multiplication with a monolithic 3-D-based scratchpad memory
DC Field | Value | Language |
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dc.contributor.author | Do, C.T. | - |
dc.contributor.author | Choi, J.H. | - |
dc.contributor.author | Lee, Y.S. | - |
dc.contributor.author | Kim, C.H. | - |
dc.contributor.author | Chung, S.W. | - |
dc.date.accessioned | 2021-12-02T06:41:49Z | - |
dc.date.available | 2021-12-02T06:41:49Z | - |
dc.date.created | 2021-08-31 | - |
dc.date.issued | 2021-06 | - |
dc.identifier.issn | 1943-0663 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/128821 | - |
dc.description.abstract | Convolutional neural networks (CNNs) are one of the most popular machine learning algorithms. The convolutional layers, which account for the most execution time of CNNs, are implemented with matrix multiplication because the convolution operation performs dot products between filters and local regions of the input. On the other hand, GPUs with thousands of cores were proven to significantly accelerate matrix multiplication, compared to CPUs with a limited number of cores, especially for large matrices. However, the current memory architecture allows only one row access at a time so that multiple accesses are necessary to read the column data of the second matrix, thus slowing down matrix multiplication. In this study, we adopt the monolithic 3-D integration for the GPU scratchpad memory, called monolithic 3-D integration (M3D) scratchpad memory (SPM), to enhance matrix multiplication. The M3D SPM allows one access to read the column data of the second matrix, similar to the case of the first matrix. The simulation results show that our M3D SPM improves the system performance by 46.3% for the 32 × 32 matrix multiplication, over the conventional 2-D SPM where the column data of the second matrix are read sequentially. © 2009-2012 IEEE. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | Enhancing matrix multiplication with a monolithic 3-D-based scratchpad memory | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Chung, S.W. | - |
dc.identifier.doi | 10.1109/LES.2020.3001954 | - |
dc.identifier.scopusid | 2-s2.0-85086724294 | - |
dc.identifier.wosid | 000655243600007 | - |
dc.identifier.bibliographicCitation | IEEE Embedded Systems Letters, v.13, no.2, pp.57 - 60 | - |
dc.relation.isPartOf | IEEE Embedded Systems Letters | - |
dc.citation.title | IEEE Embedded Systems Letters | - |
dc.citation.volume | 13 | - |
dc.citation.number | 2 | - |
dc.citation.startPage | 57 | - |
dc.citation.endPage | 60 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Software Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordAuthor | High performance | - |
dc.subject.keywordAuthor | matrix multiplication | - |
dc.subject.keywordAuthor | monolithic 3-D | - |
dc.subject.keywordAuthor | neural network | - |
dc.subject.keywordAuthor | scratchpad memory (SPM) | - |
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