PhaseNoC: Versatile Network Traffic Isolation Through TDM-Scheduled Virtual Channels
DC Field | Value | Language |
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dc.contributor.author | 이중희 | - |
dc.date.accessioned | 2022-04-10T08:40:44Z | - |
dc.date.available | 2022-04-10T08:40:44Z | - |
dc.date.created | 2022-04-08 | - |
dc.date.issued | 2016-05 | - |
dc.identifier.issn | 0278-0070 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/139879 | - |
dc.description.abstract | As multi/many-core architectures evolve, the demands on the network-on-chip (NoC) are amplified. In addition to high performance and physical scalability, the NoC is increasingly required to also provide specialized functionality, such as network virtualization, flow isolation, and quality-of-service. Although traditional architectures supporting virtual channels (VCs) offer the resources for flow partitioning and isolation, an adversarial workload can still interfere and degrade the performance of other workloads that are active in a different set of VCs. In this paper, we present PhaseNoC, a truly noninterfering VC-based architecture that adopts time-division multiplexing at the VC level. Distinct flows, or application domains, mapped to disjoint sets of VCs are isolated, both inside the router's pipeline and at the network level. Any latency overhead is minimized by appropriate scheduling of flows in separate phases of operation, irrespective of the chosen topology. When strict isolation is not required, the proposed architecture can employ opportunistic bandwidth stealing. This novel mechanism works synergistically with the baseline PhaseNoC techniques to improve the overall latency/throughput characteristics of the NoC, while still preserving performance isolation. Experimen | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | PhaseNoC: Versatile Network Traffic Isolation Through TDM-Scheduled Virtual Channels | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | 이중희 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.35, no.5, pp.844 - 857 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | - |
dc.citation.title | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | - |
dc.citation.volume | 35 | - |
dc.citation.number | 5 | - |
dc.citation.startPage | 844 | - |
dc.citation.endPage | 857 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
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