Low-Complexity and Low-Latency SVC Decoding Architecture Using Modified MAP-SP Algorithm
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Hong, S. | - |
dc.contributor.author | Kam, D. | - |
dc.contributor.author | Yun, S. | - |
dc.contributor.author | Choe, J. | - |
dc.contributor.author | Lee, N. | - |
dc.contributor.author | Lee, Y. | - |
dc.date.accessioned | 2022-06-12T01:40:20Z | - |
dc.date.available | 2022-06-12T01:40:20Z | - |
dc.date.created | 2022-06-10 | - |
dc.date.issued | 2022 | - |
dc.identifier.issn | 1549-8328 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/142085 | - |
dc.description.abstract | The compressive sensing (CS) based sparse vector coding (SVC) method is one of the promising ways for the next-generation ultra-reliable and low-latency communications. In this paper, we present advanced algorithm-hardware co-optimization schemes for realizing a cost-effective SVC decoding architecture. The previous maximum a posteriori subspace pursuit (MAP-SP) algorithm is newly modified to relax the computational overheads by applying novel residual forwarding and LLR approximation schemes. A fully-pipelined parallel hardware is also developed to support the modified decoding algorithm, reducing the overall processing latency, especially at the support identification step. In addition, an advanced least-square-problem solver is presented by utilizing the parallel Cholesky decomposer design, further reducing the decoding latency with parallel updates of support values. The implementation results from a 22nm FinFET technology showed that the fully-optimized design is 9.6 times faster while improving the area efficiency by 12 times compared to the baseline realization. © 2004-2012 IEEE. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | Low-Complexity and Low-Latency SVC Decoding Architecture Using Modified MAP-SP Algorithm | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Lee, N. | - |
dc.identifier.doi | 10.1109/TCSI.2021.3136222 | - |
dc.identifier.scopusid | 2-s2.0-85122289215 | - |
dc.identifier.bibliographicCitation | IEEE Transactions on Circuits and Systems I: Regular Papers, v.69, no.4, pp.1774 - 1787 | - |
dc.relation.isPartOf | IEEE Transactions on Circuits and Systems I: Regular Papers | - |
dc.citation.title | IEEE Transactions on Circuits and Systems I: Regular Papers | - |
dc.citation.volume | 69 | - |
dc.citation.number | 4 | - |
dc.citation.startPage | 1774 | - |
dc.citation.endPage | 1787 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordAuthor | Compressive sensing | - |
dc.subject.keywordAuthor | Parallel architecture | - |
dc.subject.keywordAuthor | Subspace pursuit | - |
dc.subject.keywordAuthor | Ultra reliable and low latency communications | - |
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