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Gate-tunable 2D memristor devices based on monolithically-integrated vertical heterojunctions
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Lee, Chul-Ho | - |
| dc.date.accessioned | 2021-08-28T02:46:51Z | - |
| dc.date.available | 2021-08-28T02:46:51Z | - |
| dc.date.created | 2021-04-22 | - |
| dc.date.issued | 2017-11-22 | - |
| dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/20986 | - |
| dc.publisher | The Korean Institute of Electrical and Electronic Material Engineers | - |
| dc.title | Gate-tunable 2D memristor devices based on monolithically-integrated vertical heterojunctions | - |
| dc.title.alternative | Gate-tunable 2D memristor devices based on monolithically-integrated vertical heterojunctions | - |
| dc.type | Conference | - |
| dc.contributor.affiliatedAuthor | Lee, Chul-Ho | - |
| dc.identifier.bibliographicCitation | Th 4th International Conference on Advanced Electromaterials (ICAE) | - |
| dc.relation.isPartOf | Th 4th International Conference on Advanced Electromaterials (ICAE) | - |
| dc.relation.isPartOf | ICAE 2017 Abstract | - |
| dc.citation.title | Th 4th International Conference on Advanced Electromaterials (ICAE) | - |
| dc.citation.conferencePlace | KO | - |
| dc.citation.conferenceDate | 2017-11-21 | - |
| dc.type.rims | CONF | - |
| dc.description.journalClass | 1 | - |
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