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A Low-Power Network-on-Chip Architecture for Tile-based Chip Multi-Processors
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Junghee Lee | - |
| dc.date.accessioned | 2021-08-28T16:37:27Z | - |
| dc.date.available | 2021-08-28T16:37:27Z | - |
| dc.date.created | 2021-04-22 | - |
| dc.date.issued | 2016-05-20 | - |
| dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/29245 | - |
| dc.publisher | Association for Computing Machinery | - |
| dc.title | A Low-Power Network-on-Chip Architecture for Tile-based Chip Multi-Processors | - |
| dc.title.alternative | A Low-Power Network-on-Chip Architecture for Tile-based Chip Multi-Processors | - |
| dc.type | Conference | - |
| dc.contributor.affiliatedAuthor | Junghee Lee | - |
| dc.identifier.bibliographicCitation | ACM International Conference on Great Lakes Symposium on VLSI | - |
| dc.relation.isPartOf | ACM International Conference on Great Lakes Symposium on VLSI | - |
| dc.relation.isPartOf | Proc. of ACM International Conference on Great Lakes Symposium on VLSI | - |
| dc.citation.title | ACM International Conference on Great Lakes Symposium on VLSI | - |
| dc.citation.conferencePlace | US | - |
| dc.citation.conferenceDate | 2016-05-18 | - |
| dc.type.rims | CONF | - |
| dc.description.journalClass | 1 | - |
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