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Self-Supervised Representation Learning for Wafer Bin Map Defect Pattern Classification

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dc.contributor.authorKahng, Hyungu-
dc.contributor.authorKim, Seoung Bum-
dc.date.accessioned2021-08-30T03:30:14Z-
dc.date.available2021-08-30T03:30:14Z-
dc.date.created2021-06-18-
dc.date.issued2021-02-
dc.identifier.issn0894-6507-
dc.identifier.urihttps://scholar.korea.ac.kr/handle/2021.sw.korea/49676-
dc.description.abstractAutomatic identification of defect patterns in wafer bin maps (WBMs) stands as a challenging problem for the semiconductor manufacturing industry. Deep convolutional neural networks have recently shown decent progress in learning spatial patterns in WBMs, but only at the expense of explicit manual supervision. Unfortunately, a clean set of labeled WBM samples is often limited in both size and quality, especially during rapid process development or early production stages. In this study, we propose a self-supervised learning framework that makes the most out of unlabeled data to learn beforehand rich visual representations for data-efficient WBM defect pattern classification. After self-supervised pre-training based on noise-contrastive estimation, the network is fine-tuned on the available labeled data to classify WBM defect patterns. We argue that self-supervised pre-training with a vast amount of unlabeled data substantially improves classification performance when labels are scarce. We demonstrate the effectiveness of our work on a real-world public WBM dataset, WM-811K. The code is available at https://github.com/hgkahng/WaPIRL.-
dc.languageEnglish-
dc.language.isoen-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleSelf-Supervised Representation Learning for Wafer Bin Map Defect Pattern Classification-
dc.typeArticle-
dc.contributor.affiliatedAuthorKim, Seoung Bum-
dc.identifier.doi10.1109/TSM.2020.3038165-
dc.identifier.scopusid2-s2.0-85098753376-
dc.identifier.wosid000615040700010-
dc.identifier.bibliographicCitationIEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, v.34, no.1, pp.74 - 86-
dc.relation.isPartOfIEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING-
dc.citation.titleIEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING-
dc.citation.volume34-
dc.citation.number1-
dc.citation.startPage74-
dc.citation.endPage86-
dc.type.rimsART-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalResearchAreaPhysics-
dc.relation.journalWebOfScienceCategoryEngineering, Manufacturing-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.relation.journalWebOfScienceCategoryPhysics, Applied-
dc.relation.journalWebOfScienceCategoryPhysics, Condensed Matter-
dc.subject.keywordAuthorFeature extraction-
dc.subject.keywordAuthorTask analysis-
dc.subject.keywordAuthorTraining-
dc.subject.keywordAuthorSemantics-
dc.subject.keywordAuthorFabrication-
dc.subject.keywordAuthorVisualization-
dc.subject.keywordAuthorDeep learning-
dc.subject.keywordAuthorWafer bin map defect pattern classification-
dc.subject.keywordAuthorsemiconductor manufacturing-
dc.subject.keywordAuthorconvolutional neural networks-
dc.subject.keywordAuthorunsupervised learning-
dc.subject.keywordAuthorself-supervised learning-
dc.subject.keywordAuthorcontrastive learning-
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