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A 7.5-GS/s 3.8-ENOB 52-mW flash ADC with clock duty cycle control in 65nm CMOS

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dc.contributor.authorHayun Cecillia Chung-
dc.date.accessioned2021-08-30T03:48:40Z-
dc.date.available2021-08-30T03:48:40Z-
dc.date.created2021-04-22-
dc.date.issued2009-06-17-
dc.identifier.urihttps://scholar.korea.ac.kr/handle/2021.sw.korea/49962-
dc.publisherIEEE-
dc.titleA 7.5-GS/s 3.8-ENOB 52-mW flash ADC with clock duty cycle control in 65nm CMOS-
dc.title.alternativeA 7.5-GS/s 3.8-ENOB 52-mW flash ADC with clock duty cycle control in 65nm CMOS-
dc.typeConference-
dc.contributor.affiliatedAuthorHayun Cecillia Chung-
dc.identifier.bibliographicCitationSymposium on VLSI Circuits 2009, pp.268 - 269-
dc.relation.isPartOfSymposium on VLSI Circuits 2009-
dc.relation.isPartOfProceedings of VLSI Circuits 2009-
dc.citation.titleSymposium on VLSI Circuits 2009-
dc.citation.startPage268-
dc.citation.endPage269-
dc.citation.conferencePlaceJA-
dc.citation.conferenceDate2009-06-16-
dc.type.rimsCONF-
dc.description.journalClass1-
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