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I/O Strength-Aware Credit Scheduler for Virtualized Environments

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dc.contributor.authorLee, Jaehak-
dc.contributor.authorYu, Heonchang-
dc.date.accessioned2021-08-30T06:42:27Z-
dc.date.available2021-08-30T06:42:27Z-
dc.date.created2021-06-19-
dc.date.issued2020-12-
dc.identifier.issn2079-9292-
dc.identifier.urihttps://scholar.korea.ac.kr/handle/2021.sw.korea/51282-
dc.description.abstractWith the evolution of cloud technology, the number of user applications is increasing, and computational workloads are becoming increasingly diverse and unpredictable. However, cloud data centers still exhibit a low I/O performance because of the scheduling policies employed, which are based on the degree of physical CPU (pCPU) occupancy. Notably, existing scheduling policies cannot guarantee good I/O performance because of the uncertainty of the extent of I/O occurrence and the lack of fine-grained workload classification. To overcome these limitations, we propose ISACS, an I/O strength-aware credit scheduler for virtualized environments. Based on the Credit2 scheduler, ISACS provides a fine-grained workload-aware scheduling technique to mitigate I/O performance degradation in virtualized environments. Further, ISACS uses the event channel mechanism in the virtualization architecture to expand the scope of the scheduling information area and measures the I/O strength of each virtual CPU (vCPU) in the run-queue. Then, ISACS allocates two types of virtual credits for all vCPUs in the run-queue to increase I/O performance and concurrently prevent CPU performance degradation. Finally, through I/O load balancing, ISACS prevents I/O-intensive vCPUs from becoming concentrated on specific cores. Our experiments show that compared with existing virtualization environments, ISACS provides a higher I/O performance with a negligible impact on CPU performance.-
dc.languageEnglish-
dc.language.isoen-
dc.publisherMDPI-
dc.subjectPERFORMANCE-
dc.subjectMECHANISM-
dc.titleI/O Strength-Aware Credit Scheduler for Virtualized Environments-
dc.typeArticle-
dc.contributor.affiliatedAuthorYu, Heonchang-
dc.identifier.doi10.3390/electronics9122107-
dc.identifier.scopusid2-s2.0-85097411731-
dc.identifier.wosid000602157800001-
dc.identifier.bibliographicCitationELECTRONICS, v.9, no.12-
dc.relation.isPartOfELECTRONICS-
dc.citation.titleELECTRONICS-
dc.citation.volume9-
dc.citation.number12-
dc.type.rimsART-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaComputer Science-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalResearchAreaPhysics-
dc.relation.journalWebOfScienceCategoryComputer Science, Information Systems-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.relation.journalWebOfScienceCategoryPhysics, Applied-
dc.subject.keywordPlusPERFORMANCE-
dc.subject.keywordPlusMECHANISM-
dc.subject.keywordAuthorcloud-
dc.subject.keywordAuthorvirtualization-
dc.subject.keywordAuthorhypervisor-
dc.subject.keywordAuthorscheduler-
dc.subject.keywordAuthorI/O performance-
dc.subject.keywordAuthorworkload aware-
dc.subject.keywordAuthorresource management-
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