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Delay analysis in the discrete-time multi-server queue with batch arrivals of packets having deterministic length

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dc.contributor.authorLee, S.-
dc.contributor.authorKim, B.-
dc.contributor.authorKang, J.-
dc.date.accessioned2021-08-30T09:04:07Z-
dc.date.available2021-08-30T09:04:07Z-
dc.date.created2021-06-19-
dc.date.issued2020-11-12-
dc.identifier.issn0013-5194-
dc.identifier.urihttps://scholar.korea.ac.kr/handle/2021.sw.korea/51813-
dc.description.abstractThis work considers a discrete-time multi-server queue with batch arrivals of packets having a deterministic length. By a novel analysis, the packet delay distribution is computed with a very light computational workload.-
dc.languageEnglish-
dc.language.isoen-
dc.publisherINST ENGINEERING TECHNOLOGY-IET-
dc.titleDelay analysis in the discrete-time multi-server queue with batch arrivals of packets having deterministic length-
dc.typeArticle-
dc.contributor.affiliatedAuthorKim, B.-
dc.identifier.doi10.1049/el.2020.1560-
dc.identifier.scopusid2-s2.0-85095706305-
dc.identifier.wosid000588389600012-
dc.identifier.bibliographicCitationELECTRONICS LETTERS, v.56, no.23, pp.1250 - 1253-
dc.relation.isPartOfELECTRONICS LETTERS-
dc.citation.titleELECTRONICS LETTERS-
dc.citation.volume56-
dc.citation.number23-
dc.citation.startPage1250-
dc.citation.endPage1253-
dc.type.rimsART-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
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