Filter cache: filtering useless cache blocks for a small but efficient shared last-level cache
DC Field | Value | Language |
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dc.contributor.author | Bae, Han Jun | - |
dc.contributor.author | Choi, Lynn | - |
dc.date.accessioned | 2021-08-30T13:01:59Z | - |
dc.date.available | 2021-08-30T13:01:59Z | - |
dc.date.created | 2021-06-18 | - |
dc.date.issued | 2020-10 | - |
dc.identifier.issn | 0920-8542 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/52663 | - |
dc.description.abstract | Although the shared last-level cache (SLLC) occupies a significant portion of multicore CPU chip die area, more than 59% of SLLC cache blocks are not reused during their lifetime. If we can filter out these useless blocks from SLLC, we can effectively reduce the size of SLLC without sacrificing performance. For this purpose, we classify the reuse of cache blocks into temporal and spatial reuse and further analyze the reuse by using reuse interval and reuse count. From our experimentation, we found that most of spatially reused cache blocks are reused only once with short reuse interval, so it is inefficient to manage them in SLLC. In this paper, we propose a new small additional cache called Filter Cache to the SLLC, which cannot only check the temporal reuse but also can prevent spatially reused blocks from entering the SLLC. Thus, we do not maintain data for non-reused blocks and spatially reused blocks in the SLLC, dramatically reducing the size of the SLLC. Through our detailed simulation on PARSEC benchmarks, we show that our new SLLC design with Filter Cache exhibits comparable performance to the conventional SLLC with only 24.21% of SLLC area across a variety of different workloads. This is achieved by its faster access and high reuse rates in the small SLLC with Filter Cache. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | SPRINGER | - |
dc.title | Filter cache: filtering useless cache blocks for a small but efficient shared last-level cache | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Choi, Lynn | - |
dc.identifier.doi | 10.1007/s11227-020-03177-2 | - |
dc.identifier.scopusid | 2-s2.0-85078739952 | - |
dc.identifier.wosid | 000510074700004 | - |
dc.identifier.bibliographicCitation | JOURNAL OF SUPERCOMPUTING, v.76, no.10, pp.7521 - 7544 | - |
dc.relation.isPartOf | JOURNAL OF SUPERCOMPUTING | - |
dc.citation.title | JOURNAL OF SUPERCOMPUTING | - |
dc.citation.volume | 76 | - |
dc.citation.number | 10 | - |
dc.citation.startPage | 7521 | - |
dc.citation.endPage | 7544 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Theory & Methods | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordAuthor | Shared last-level cache | - |
dc.subject.keywordAuthor | Reuse rate | - |
dc.subject.keywordAuthor | Temporal reuse | - |
dc.subject.keywordAuthor | Spatial reuse | - |
dc.subject.keywordAuthor | Multicore CPU | - |
dc.subject.keywordAuthor | Cache organization | - |
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