A novel warp scheduling scheme considering long-latency operations for high-performance GPUs
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Cong Thuan Do | - |
dc.contributor.author | Choi, Hong Jun | - |
dc.contributor.author | Chung, Sung Woo | - |
dc.contributor.author | Kim, Cheol Hong | - |
dc.date.accessioned | 2021-08-31T04:55:11Z | - |
dc.date.available | 2021-08-31T04:55:11Z | - |
dc.date.created | 2021-06-18 | - |
dc.date.issued | 2020-04 | - |
dc.identifier.issn | 0920-8542 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/56829 | - |
dc.description.abstract | Graphics processing units (GPUs) have become one of the best platforms for exploiting the plentiful thread-level parallelism of applications. However, GPUs continue to underutilize their hardware resources for optimizing the performance of numerous general-purpose applications. One primary reason for this is the inefficiency of existing warp schedulers in hiding long-latency operations such as global loads and stores. This study proposes a long-latency operation-based warp scheduler to improve GPU performance. In the proposed warp scheduler, warps are partitioned into different pools based on the characteristics of instructions that are subsequently executed. Specifically, this warp scheduler uses warps that are likely waiting for long-latency operations for a guiding role. Meanwhile, other warps perform filling roles (i.e., to overlap the latencies caused by the guiding warps). Our experimental results demonstrate that the proposed warp scheduler improves GPU performance by 24.4% on average as compared to the conventional warp scheduler. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | SPRINGER | - |
dc.title | A novel warp scheduling scheme considering long-latency operations for high-performance GPUs | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Chung, Sung Woo | - |
dc.identifier.doi | 10.1007/s11227-019-03091-2 | - |
dc.identifier.scopusid | 2-s2.0-85075347426 | - |
dc.identifier.wosid | 000498144400001 | - |
dc.identifier.bibliographicCitation | JOURNAL OF SUPERCOMPUTING, v.76, no.4, pp.3043 - 3062 | - |
dc.relation.isPartOf | JOURNAL OF SUPERCOMPUTING | - |
dc.citation.title | JOURNAL OF SUPERCOMPUTING | - |
dc.citation.volume | 76 | - |
dc.citation.number | 4 | - |
dc.citation.startPage | 3043 | - |
dc.citation.endPage | 3062 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Theory & Methods | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordAuthor | GPGPU | - |
dc.subject.keywordAuthor | Performance | - |
dc.subject.keywordAuthor | Memory latency | - |
dc.subject.keywordAuthor | Utilization | - |
dc.subject.keywordAuthor | Warp scheduling | - |
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