Hi-End: Hierarchical, Endurance-Aware STT-MRAM-Based Register File for Energy-Efficient GPUs
DC Field | Value | Language |
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dc.contributor.author | Jeon, Won | - |
dc.contributor.author | Park, Jun Hyun | - |
dc.contributor.author | Kim, Yoonsoo | - |
dc.contributor.author | Koo, Gunjae | - |
dc.contributor.author | Ro, Won Woo | - |
dc.date.accessioned | 2021-08-31T16:00:41Z | - |
dc.date.available | 2021-08-31T16:00:41Z | - |
dc.date.created | 2021-06-19 | - |
dc.date.issued | 2020 | - |
dc.identifier.issn | 2169-3536 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/58950 | - |
dc.description.abstract | Modern Graphics Processing Units (GPUs) require large hardware resources for massive parallel thread executions. In particular, modern GPUs have a large register file composed of Static Random Access Memory (SRAM). Due to the high leakage current of SRAM, the register file consumes approximately 20% of the total GPU energy. The energy efficiency of the register file becomes more critical as the throughput of GPUs increases. For more energy-efficient GPUs, the usage of non-volatile memory such as Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) as the GPU register file has been studied extensively. STT-MRAM requires a lower leakage current compared to SRAM and provides an appropriate read performance. However, using STT-MRAM directly in the GPU register file causes problems in performance and endurance because of complicated write procedures and material characteristics. To overcome these challenges, we propose a novel register file architecture and its management system for GPUs, named Hi-End, which exploits the data locality and compressibility of the register file. For STT-MRAM-based GPU register files, Hi-End increases the data write performance and endurance by caching and data compression, respectively. In our evaluation, Hi-End enhances the energy efficiency of a GPU register file by 70.02% and reduces the write operations by up to 95.98% with negligible performance degradation compared to SRAM-based register files. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | RAM | - |
dc.title | Hi-End: Hierarchical, Endurance-Aware STT-MRAM-Based Register File for Energy-Efficient GPUs | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Koo, Gunjae | - |
dc.identifier.doi | 10.1109/ACCESS.2020.3008719 | - |
dc.identifier.scopusid | 2-s2.0-85089217359 | - |
dc.identifier.wosid | 000551825500001 | - |
dc.identifier.bibliographicCitation | IEEE ACCESS, v.8, pp.127768 - 127780 | - |
dc.relation.isPartOf | IEEE ACCESS | - |
dc.citation.title | IEEE ACCESS | - |
dc.citation.volume | 8 | - |
dc.citation.startPage | 127768 | - |
dc.citation.endPage | 127780 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Telecommunications | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Information Systems | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Telecommunications | - |
dc.subject.keywordPlus | RAM | - |
dc.subject.keywordAuthor | Graphics processing unit | - |
dc.subject.keywordAuthor | register file | - |
dc.subject.keywordAuthor | spin-transfer torque magnetic random access memory | - |
dc.subject.keywordAuthor | data compression | - |
dc.subject.keywordAuthor | energy efficiency | - |
dc.subject.keywordAuthor | endurance | - |
dc.subject.keywordAuthor | chip area | - |
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