A Delta Sigma Modulator-Based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for Phase-Locked Loop Bandwidth
- Authors
- Bae, Sang-Geun; Hwang, Sewook; Song, Junyoung; Lee, Yeonho; Kim, Chulwoo
- Issue Date
- 2월-2019
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- EMI reduction; PLL; spread-spectrum clock; SSCG; digital compensation
- Citation
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.66, no.2, pp.192 - 196
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
- Volume
- 66
- Number
- 2
- Start Page
- 192
- End Page
- 196
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/67771
- DOI
- 10.1109/TCSII.2018.2846690
- ISSN
- 1549-7747
- Abstract
- A spread-spectrum clock generator (SSCG) is an essential building block for reducing electromagnetic interference (EMI) in a system-on-a-chip without shielding the device that increases the system cost and weight. In a AI modulator (DSM)-based SSCG, EMI reduction is degraded by attenuating the harmonic components of the generated profile owing to the phase-locked loop bandwidth (f(LBW)).This brief proposes a DSM-based SSCG with a digital compensator to maximize EMI reduction with a triangular profile. By adaptively reconfiguring the gains of the digital compensator, the proposed SSCG maintains the EMI reduction regardless of f(LBw) variations. The EMI reduction is improved by 2.17 dB at 1.35 GHz with the lowest f(LBw). A prototype of the proposed SSCG is fabricated using 65-nm CMOS technology. The measured RMS jitter and power consumption are is 2.47 ps and 7 mW, respectively and the die occupies 0.292 mm(2).
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Collections - College of Engineering > School of Electrical Engineering > 1. Journal Articles
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