Pipelined Squarer for Unsigned Integers of Up to 12 Bits
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Choi, Seongjin | - |
dc.contributor.author | Oh, Hyeong-Cheol | - |
dc.date.accessioned | 2021-09-02T14:46:50Z | - |
dc.date.available | 2021-09-02T14:46:50Z | - |
dc.date.created | 2021-06-16 | - |
dc.date.issued | 2018-03 | - |
dc.identifier.issn | 1745-1361 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/77265 | - |
dc.description.abstract | This paper proposes and analyzes a pipelining scheme for a hardware squarer that can square unsigned integers of up to 12 bits. Each stage is designed and adjusted such that stage delays are well balanced and that the critical path delay of the design does not exceed the reference value which is set up based on the analysis. The resultant design has the critical path delay of approximately 3.5 times a full-adder delay. In an implementation using an Intel Stratix V FPGA, the design operates at approximately 23% higher frequency than the comparable pipelined squarer provided in the Intel library. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG | - |
dc.title | Pipelined Squarer for Unsigned Integers of Up to 12 Bits | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Choi, Seongjin | - |
dc.contributor.affiliatedAuthor | Oh, Hyeong-Cheol | - |
dc.identifier.doi | 10.1587/transinf.2017EDL8229 | - |
dc.identifier.scopusid | 2-s2.0-85042636569 | - |
dc.identifier.wosid | 000431772500026 | - |
dc.identifier.bibliographicCitation | IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, v.E101D, no.3, pp.795 - 798 | - |
dc.relation.isPartOf | IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS | - |
dc.citation.title | IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS | - |
dc.citation.volume | E101D | - |
dc.citation.number | 3 | - |
dc.citation.startPage | 795 | - |
dc.citation.endPage | 798 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Information Systems | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Software Engineering | - |
dc.subject.keywordAuthor | squarer | - |
dc.subject.keywordAuthor | high-speed pipelining | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
(02841) 서울특별시 성북구 안암로 14502-3290-1114
COPYRIGHT © 2021 Korea University. All Rights Reserved.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.