합성곱 신경망을 이용한 웨이퍼 맵 기반 불량 탐지
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 박재선 | - |
dc.contributor.author | 김준홍 | - |
dc.contributor.author | 김형석 | - |
dc.contributor.author | 모경현 | - |
dc.contributor.author | 강필성 | - |
dc.date.accessioned | 2021-09-02T18:09:30Z | - |
dc.date.available | 2021-09-02T18:09:30Z | - |
dc.date.created | 2021-06-17 | - |
dc.date.issued | 2018 | - |
dc.identifier.issn | 1225-0988 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/79117 | - |
dc.description.abstract | The Electrical die sorting (EDS) test is performed to discriminate defective wafers for the purpose of improving the yield of the wafers during the semiconductor manufacturing process, and wafer maps are generated as a result. Semiconductor manufacturing process and equipment engineers use the patterns of the wafer map based on their knowledge to judge the defective wafer and estimate the cause. We use convolutional neural network which demonstrate good performance in the image classification. The convolutional neural network is used as a classification model of which the image of wafer map itself as input and whether the image is good or bad as output. While previous studies have used hand-crafted features for wafer map-based fault detection, the methodology used in this study is that the convolutional neural network learns the features useful for classification, it has the advantage of integrating knowledge. We show that the proposed classifier has better prediction accuracy than the conventional machine learning based techniques such as multilayer perceptron and random forest empirically by experiments on the data collected in the actual semiconductor manufacturing process. | - |
dc.language | Korean | - |
dc.language.iso | ko | - |
dc.publisher | 대한산업공학회 | - |
dc.title | 합성곱 신경망을 이용한 웨이퍼 맵 기반 불량 탐지 | - |
dc.title.alternative | Wafer Map-based Defect Detection Using Convolutional Neural Networks | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | 강필성 | - |
dc.identifier.doi | 10.7232/JKIIE.2018.44.4.249 | - |
dc.identifier.bibliographicCitation | 대한산업공학회지, v.44, no.4, pp.249 - 258 | - |
dc.relation.isPartOf | 대한산업공학회지 | - |
dc.citation.title | 대한산업공학회지 | - |
dc.citation.volume | 44 | - |
dc.citation.number | 4 | - |
dc.citation.startPage | 249 | - |
dc.citation.endPage | 258 | - |
dc.type.rims | ART | - |
dc.identifier.kciid | ART002373524 | - |
dc.description.journalClass | 2 | - |
dc.description.journalRegisteredClass | kci | - |
dc.subject.keywordAuthor | Semiconductor Manufacturing | - |
dc.subject.keywordAuthor | Wafer Map | - |
dc.subject.keywordAuthor | EDS test | - |
dc.subject.keywordAuthor | Convolutional Neural Network | - |
dc.subject.keywordAuthor | Deep Learning | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
(02841) 서울특별시 성북구 안암로 14502-3290-1114
COPYRIGHT © 2021 Korea University. All Rights Reserved.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.