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A 0.17-1.4GHz Low-Jitter All Digital DLL with TDC-based DCC using Pulse Width Detection Scheme
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | KIM, Chulwoo | - |
| dc.date.accessioned | 2021-09-02T20:34:14Z | - |
| dc.date.available | 2021-09-02T20:34:14Z | - |
| dc.date.created | 2021-04-22 | - |
| dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/80541 | - |
| dc.publisher | European Solid-State Circuits Conference | - |
| dc.title | A 0.17-1.4GHz Low-Jitter All Digital DLL with TDC-based DCC using Pulse Width Detection Scheme | - |
| dc.type | Conference | - |
| dc.contributor.affiliatedAuthor | KIM, Chulwoo | - |
| dc.identifier.bibliographicCitation | European Solid-State Circuits Conference, pp.82 - 85 | - |
| dc.relation.isPartOf | European Solid-State Circuits Conference | - |
| dc.citation.title | European Solid-State Circuits Conference | - |
| dc.citation.startPage | 82 | - |
| dc.citation.endPage | 85 | - |
| dc.citation.conferencePlace | UK | - |
| dc.citation.conferenceDate | 2008-09-15 | - |
| dc.type.rims | CONF | - |
| dc.description.journalClass | 1 | - |
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