A 5-GHz Subsampling PLL-Based Spread-Spectrum Clock Generator by Calibrating the Frequency Deviation
- Authors
- Bae, Sang-Geun; Kim, Gyungmin; Kim, Chulwoo
- Issue Date
- 10월-2017
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Auto-calibration; spread-spectrum clock generator (SSCG); subsampling phase-locked loop (SSPLL)
- Citation
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.64, no.10, pp.1132 - 1136
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
- Volume
- 64
- Number
- 10
- Start Page
- 1132
- End Page
- 1136
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/82117
- DOI
- 10.1109/TCSII.2016.2624759
- ISSN
- 1549-7747
- Abstract
- This brief presents a spread-spectrum clock generator (SSCG) based on a subsampling phase-locked loop (SSPLL) by calibrating the spreading ratio. The proposed SSCG has a low jitter performance owing to the low in-band phase noise performance of the SSPLL. To achieve a spread-spectrum clocking, the direct voltage-controlled oscillator modulation method is used owing to the absence of a frequency divider. However, the spreading ratio (d) can be varied by process, voltage, and temperature variations. Automatic calibration technique is proposed for a 5000-ppm spreading ratio at 5 GHz. The proposed SSCG achieves a 21-dB electromagnetic interference reduction, has a -104-dBc/Hz phase noise at 200-kHz offset, and consumes 7 mW and occupies a 0.39-mm(2) area in a 65-nm CMOS process.
- Files in This Item
- There are no files associated with this item.
- Appears in
Collections - College of Engineering > School of Electrical Engineering > 1. Journal Articles
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.