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A 1.62-5.4-Gb/s Receiver for DisplayPort Version 1.2a With Adaptive Equalization and Referenceless Frequency Acquisition Techniques

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dc.contributor.authorHwang, Sewook-
dc.contributor.authorSong, Junyoung-
dc.contributor.authorLee, Yeonho-
dc.contributor.authorKim, Chulwoo-
dc.date.accessioned2021-09-03T01:00:58Z-
dc.date.available2021-09-03T01:00:58Z-
dc.date.created2021-06-18-
dc.date.issued2017-10-
dc.identifier.issn1549-8328-
dc.identifier.urihttps://scholar.korea.ac.kr/handle/2021.sw.korea/82157-
dc.description.abstractWe present a 1.62-5.4-Gb/s receiver for DisplayPort version 1.2a and propose an adaptive equalizer (EQ) with a peak-level comparison technique for eye measurement. A single comparator and an up/down unmatched-current charge pump are used to realize a simpler EQ architecture with low power dissipation. A referenceless frequency acquisition technique is also proposed. A time-to-digital converter-based pulsewidth detector supports the referenceless frequency acquisition within the range of 1.62-5.4 Gb/s. An XOR-gate-embedded charge pump and a half-rate linear phase detector were used to improve the jitter tolerance (JTOL) performance. The measured eye opening of the proposed EQ at 5.4 Gb/s was 0.68 UI with a -20-dB loss channel. The proposed receiver passed all the JTOL tests of the DisplayPort compliance specification version 1.2b. The power consumption of the receiver was 36.8 mW at 5.4 Gb/s. The receiver occupied a core area of 0.265 mm(2) using 65-nm CMOS process technology.-
dc.languageEnglish-
dc.language.isoen-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectPHASE-
dc.subjectCMOS-
dc.titleA 1.62-5.4-Gb/s Receiver for DisplayPort Version 1.2a With Adaptive Equalization and Referenceless Frequency Acquisition Techniques-
dc.typeArticle-
dc.contributor.affiliatedAuthorKim, Chulwoo-
dc.identifier.doi10.1109/TCSI.2017.2695612-
dc.identifier.scopusid2-s2.0-85019835278-
dc.identifier.wosid000413831600005-
dc.identifier.bibliographicCitationIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.64, no.10, pp.2691 - 2702-
dc.relation.isPartOfIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS-
dc.citation.titleIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS-
dc.citation.volume64-
dc.citation.number10-
dc.citation.startPage2691-
dc.citation.endPage2702-
dc.type.rimsART-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordPlusPHASE-
dc.subject.keywordPlusCMOS-
dc.subject.keywordAuthorReceiver (Rx)-
dc.subject.keywordAuthoradaptive equalizer (EQ)-
dc.subject.keywordAuthorreferenceless-
dc.subject.keywordAuthorclock and data recovery (CDR)-
dc.subject.keywordAuthorfrequency detector-
dc.subject.keywordAuthorDisplayPort-
dc.subject.keywordAuthorcompliance test-
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