Negative Capacitance FinFET With Sub-20-mV/decade Subthreshold Slope and Minimal Hysteresis of 0.48 V
DC Field | Value | Language |
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dc.contributor.author | Ko, Eunah | - |
dc.contributor.author | Lee, Jae Woo | - |
dc.contributor.author | Shin, Changhwan | - |
dc.date.accessioned | 2021-09-03T07:41:41Z | - |
dc.date.available | 2021-09-03T07:41:41Z | - |
dc.date.created | 2021-06-16 | - |
dc.date.issued | 2017-04 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/83926 | - |
dc.description.abstract | In this letter, an n-type short-channel negative capacitance FinFET (NC-FinFET) with a hysteresis window of 0.48 V, an on-/off-current ratio of 10(7), and a sub20- mV/decade average subthreshold slope (SSavg) that is intended to overcome the Boltzmann limit (i. e., the physical limit in the SS, which is 60 mV/decade at 300 K), is experimentally demonstrated vs. a baseline FinFET with an SSavg of similar to 105 mV/decade. In our testing, we confirmed that the large hysteresis window in a short-channel NC-FinFET can be suppressed by using an appropriate source/drain extension length (L-ext). As Lext in the NC-FinFET is increased, the gate-to-source/drain capacitance (C-GS/C-GD) decreased and the hysteresis window narrows. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Negative Capacitance FinFET With Sub-20-mV/decade Subthreshold Slope and Minimal Hysteresis of 0.48 V | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Lee, Jae Woo | - |
dc.identifier.doi | 10.1109/LED.2017.2672967 | - |
dc.identifier.scopusid | 2-s2.0-85017580217 | - |
dc.identifier.wosid | 000398905400002 | - |
dc.identifier.bibliographicCitation | IEEE ELECTRON DEVICE LETTERS, v.38, no.4, pp.418 - 421 | - |
dc.relation.isPartOf | IEEE ELECTRON DEVICE LETTERS | - |
dc.citation.title | IEEE ELECTRON DEVICE LETTERS | - |
dc.citation.volume | 38 | - |
dc.citation.number | 4 | - |
dc.citation.startPage | 418 | - |
dc.citation.endPage | 421 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordAuthor | Steep switching | - |
dc.subject.keywordAuthor | negative capacitance FinFET | - |
dc.subject.keywordAuthor | ferroelectric capacitor | - |
dc.subject.keywordAuthor | S/D extension length (L-ext) | - |
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