Optimal Memory Size Formula for Moving-Average Digital Phase-Locked Loop
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Ahn, Choon Ki | - |
dc.contributor.author | Shi, Peng | - |
dc.contributor.author | You, Sung Hyun | - |
dc.date.accessioned | 2021-09-03T16:07:57Z | - |
dc.date.available | 2021-09-03T16:07:57Z | - |
dc.date.created | 2021-06-16 | - |
dc.date.issued | 2016-12 | - |
dc.identifier.issn | 1070-9908 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/86623 | - |
dc.description.abstract | This letter proposes a new moving-average form of digital phase-locked loop (DPLL) that uses the average value of measurements on a memory horizon and the correction term to estimate phase information. This ensures the desired unbiasedness property for the phase information. A new formula for the optimal memory size of the proposed DPLL with minimization of the expected squared phase error is established. A numerical example is given to show that the developed DPLL has superior robustness against quantization and incorrect noise compared to the existing DPLLs. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | FILTERS | - |
dc.subject | ALGORITHM | - |
dc.subject | SYSTEMS | - |
dc.title | Optimal Memory Size Formula for Moving-Average Digital Phase-Locked Loop | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Ahn, Choon Ki | - |
dc.identifier.doi | 10.1109/LSP.2016.2623520 | - |
dc.identifier.scopusid | 2-s2.0-85012925180 | - |
dc.identifier.wosid | 000389339700002 | - |
dc.identifier.bibliographicCitation | IEEE SIGNAL PROCESSING LETTERS, v.23, no.12, pp.1844 - 1847 | - |
dc.relation.isPartOf | IEEE SIGNAL PROCESSING LETTERS | - |
dc.citation.title | IEEE SIGNAL PROCESSING LETTERS | - |
dc.citation.volume | 23 | - |
dc.citation.number | 12 | - |
dc.citation.startPage | 1844 | - |
dc.citation.endPage | 1847 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | FILTERS | - |
dc.subject.keywordPlus | ALGORITHM | - |
dc.subject.keywordPlus | SYSTEMS | - |
dc.subject.keywordAuthor | Digital phase-locked loop (DPLL) | - |
dc.subject.keywordAuthor | moving average | - |
dc.subject.keywordAuthor | optimal memory size | - |
dc.subject.keywordAuthor | robustness | - |
dc.subject.keywordAuthor | unbiasedness | - |
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