Unbalanced Layout Method for the 4H-SiC JBS Diode Offering Improved Tradeoff between Leakage Current and ON-Resistance

Abstract

Two critical issues in the electrical characteristics of the 4H-SiC junction barrier Schottky (JBS) diode are the OFF-state leakage current and the ON-resistance, which are in a tradeoff relationship. To overcome the limitations resulting from these electrical characteristics, an unbalanced layout method is proposed in this letter. It can be verified that the difference in the mobility at the sides and at the center of the chip is because of the temperature distribution in JBS discrete devices. Hence, a JBS discrete device chip using the unbalanced layout method is fabricated, which has a higher ratio of Schottky barrier diode, which is ratio of the junction area: Schottky area in one cell, at the sides of the chip than at the center. The OFF-state leakage current of the unbalanced layout design is 100 times smaller than that of the reference model, for the same ON-state current.