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A New Approach on Design of a Digital Phase-Locked Loop

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dc.contributor.authorAhn, Choon Ki-
dc.contributor.authorShi, Peng-
dc.contributor.authorYou, Sung Hyun-
dc.date.accessioned2021-09-04T00:19:12Z-
dc.date.available2021-09-04T00:19:12Z-
dc.date.created2021-06-18-
dc.date.issued2016-05-
dc.identifier.issn1070-9908-
dc.identifier.urihttps://scholar.korea.ac.kr/handle/2021.sw.korea/88848-
dc.description.abstractIn this letter, we propose a new approach to the design of a digital phase-locked loop (DPLL) with a finite impulse response (FIR) structure, deadbeat property, and H-infinity performance. This DPLL is called the deadbeat H-infinity FIR DPLL (DHFDPLL). The proposed DHFDPLL ensures the H-infinity performance against incorrect information on noise and has intrinsic robustness against quantization effects because of the FIR structure. Demonstrative simulations are provided to show that the DHFDPLL exhibits excellent robustness against effects of incorrect noise and quantization compared with the existing DPLLs.-
dc.languageEnglish-
dc.language.isoen-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectFILTER DESIGN-
dc.subjectTIME-
dc.subjectSYSTEMS-
dc.subjectDELAY-
dc.subjectMODEL-
dc.subjectL(2)-
dc.titleA New Approach on Design of a Digital Phase-Locked Loop-
dc.typeArticle-
dc.contributor.affiliatedAuthorAhn, Choon Ki-
dc.identifier.doi10.1109/LSP.2016.2542291-
dc.identifier.scopusid2-s2.0-84964329205-
dc.identifier.wosid000374302200002-
dc.identifier.bibliographicCitationIEEE SIGNAL PROCESSING LETTERS, v.23, no.5, pp.600 - 604-
dc.relation.isPartOfIEEE SIGNAL PROCESSING LETTERS-
dc.citation.titleIEEE SIGNAL PROCESSING LETTERS-
dc.citation.volume23-
dc.citation.number5-
dc.citation.startPage600-
dc.citation.endPage604-
dc.type.rimsART-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordPlusFILTER DESIGN-
dc.subject.keywordPlusTIME-
dc.subject.keywordPlusSYSTEMS-
dc.subject.keywordPlusDELAY-
dc.subject.keywordPlusMODEL-
dc.subject.keywordPlusL(2)-
dc.subject.keywordAuthorDigital phase-locked loop (DPLL)-
dc.subject.keywordAuthordead-beat property-
dc.subject.keywordAuthorfinite impulse response (FIR) structure-
dc.subject.keywordAuthorH-infinity performance-
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