A New Approach on Design of a Digital Phase-Locked Loop
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Ahn, Choon Ki | - |
dc.contributor.author | Shi, Peng | - |
dc.contributor.author | You, Sung Hyun | - |
dc.date.accessioned | 2021-09-04T00:19:12Z | - |
dc.date.available | 2021-09-04T00:19:12Z | - |
dc.date.created | 2021-06-18 | - |
dc.date.issued | 2016-05 | - |
dc.identifier.issn | 1070-9908 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/88848 | - |
dc.description.abstract | In this letter, we propose a new approach to the design of a digital phase-locked loop (DPLL) with a finite impulse response (FIR) structure, deadbeat property, and H-infinity performance. This DPLL is called the deadbeat H-infinity FIR DPLL (DHFDPLL). The proposed DHFDPLL ensures the H-infinity performance against incorrect information on noise and has intrinsic robustness against quantization effects because of the FIR structure. Demonstrative simulations are provided to show that the DHFDPLL exhibits excellent robustness against effects of incorrect noise and quantization compared with the existing DPLLs. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | FILTER DESIGN | - |
dc.subject | TIME | - |
dc.subject | SYSTEMS | - |
dc.subject | DELAY | - |
dc.subject | MODEL | - |
dc.subject | L(2) | - |
dc.title | A New Approach on Design of a Digital Phase-Locked Loop | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Ahn, Choon Ki | - |
dc.identifier.doi | 10.1109/LSP.2016.2542291 | - |
dc.identifier.scopusid | 2-s2.0-84964329205 | - |
dc.identifier.wosid | 000374302200002 | - |
dc.identifier.bibliographicCitation | IEEE SIGNAL PROCESSING LETTERS, v.23, no.5, pp.600 - 604 | - |
dc.relation.isPartOf | IEEE SIGNAL PROCESSING LETTERS | - |
dc.citation.title | IEEE SIGNAL PROCESSING LETTERS | - |
dc.citation.volume | 23 | - |
dc.citation.number | 5 | - |
dc.citation.startPage | 600 | - |
dc.citation.endPage | 604 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | FILTER DESIGN | - |
dc.subject.keywordPlus | TIME | - |
dc.subject.keywordPlus | SYSTEMS | - |
dc.subject.keywordPlus | DELAY | - |
dc.subject.keywordPlus | MODEL | - |
dc.subject.keywordPlus | L(2) | - |
dc.subject.keywordAuthor | Digital phase-locked loop (DPLL) | - |
dc.subject.keywordAuthor | dead-beat property | - |
dc.subject.keywordAuthor | finite impulse response (FIR) structure | - |
dc.subject.keywordAuthor | H-infinity performance | - |
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