An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Hwang, Sewook | - |
dc.contributor.author | Song, Junyoung | - |
dc.contributor.author | Bae, Sang-Geun | - |
dc.contributor.author | Lee, Yeonho | - |
dc.contributor.author | Kim, Chulwoo | - |
dc.date.accessioned | 2021-09-04T02:13:13Z | - |
dc.date.available | 2021-09-04T02:13:13Z | - |
dc.date.created | 2021-06-16 | - |
dc.date.issued | 2016-03 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/89382 | - |
dc.description.abstract | An add-on type real-time jitter tolerance enhancer (JTE) is presented in this paper. The proposed JTE can improve high-frequency jitter tolerance (JTOL) by using a real-time phase alignment scheme. A mathematical analysis for an advanced bit error rate (BER) prediction method is also introduced. The proposed circuit is applicable to various types of receivers, such as referenceless receivers, receivers with a reference clock source, and source-synchronous receivers. The referenceless receiver with the proposed JTE achieved an out-of-band JTOL of 0.71 UIpp at 100 MHz with <10(-12) BER. This is 196% higher than a conventional receiver without the JTE. The source-synchronous receiver with the proposed JTE achieved 0.92 UIpp at 300 MHz with <10(-12) BER. Total core areas of the receiver and JTE are 0.19 and 0.07 mm(2) in a 0.13-mu m CMOS process, respectively. The power consumption of the receiver is 38 mW at 5.4 Gbit/s, and the JTE dissipates 22 mW. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | PHASE-DETECTOR | - |
dc.subject | CMOS | - |
dc.title | An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Chulwoo | - |
dc.identifier.doi | 10.1109/TVLSI.2015.2435026 | - |
dc.identifier.scopusid | 2-s2.0-84931086233 | - |
dc.identifier.wosid | 000371932100025 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.3, pp.1092 - 1103 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.title | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.volume | 24 | - |
dc.citation.number | 3 | - |
dc.citation.startPage | 1092 | - |
dc.citation.endPage | 1103 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | PHASE-DETECTOR | - |
dc.subject.keywordPlus | CMOS | - |
dc.subject.keywordAuthor | Bit error rate (BER) | - |
dc.subject.keywordAuthor | jitter tolerance (JTOL) | - |
dc.subject.keywordAuthor | real-time jitter tolerance enhancer (JTE) | - |
dc.subject.keywordAuthor | receiver (Rx) | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
(02841) 서울특별시 성북구 안암로 14502-3290-1114
COPYRIGHT © 2021 Korea University. All Rights Reserved.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.