All-Digital Duty-Cycle Corrector With a Wide Duty Correction Range for DRAM Applications
DC Field | Value | Language |
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dc.contributor.author | Jeong, Chan-Hui | - |
dc.contributor.author | Abdullah, Ammar | - |
dc.contributor.author | Min, Young-Jae | - |
dc.contributor.author | Hwang, In-Chul | - |
dc.contributor.author | Kim, Soo-Won | - |
dc.date.accessioned | 2021-09-04T04:38:03Z | - |
dc.date.available | 2021-09-04T04:38:03Z | - |
dc.date.created | 2021-06-18 | - |
dc.date.issued | 2016-01 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/90005 | - |
dc.description.abstract | An all-digital duty-cycle corrector with a wide duty correction range and fast correction time is hereby presented. The proposed corrector uses a 1-bit digital duty-cycle detector with a time-to-digital converter, and it achieves a duty correction range between 10% and 90% with a low pressure, volume, and temperature variation. The test chip was fabricated using a 0.13-mu m CMOS process, and it occupies an area of 0.059 mm(2). The correction cycle is a 14 cycles and the duty-cycle error is below +/- 1.4%. At an operating frequency of 1 GHz, the power dissipation and peak-to-peak jitter are measured at 5.6 mW and 20.5 ps, respectively. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | LOOP | - |
dc.title | All-Digital Duty-Cycle Corrector With a Wide Duty Correction Range for DRAM Applications | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Soo-Won | - |
dc.identifier.doi | 10.1109/TVLSI.2015.2394486 | - |
dc.identifier.scopusid | 2-s2.0-84923096335 | - |
dc.identifier.wosid | 000367261900037 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.1, pp.363 - 367 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.title | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.volume | 24 | - |
dc.citation.number | 1 | - |
dc.citation.startPage | 363 | - |
dc.citation.endPage | 367 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | LOOP | - |
dc.subject.keywordAuthor | DRAM | - |
dc.subject.keywordAuthor | duty-cycle corrector (DCC) | - |
dc.subject.keywordAuthor | successive approximation register (SAR) controller | - |
dc.subject.keywordAuthor | Digital comparator | - |
dc.subject.keywordAuthor | double data rate | - |
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