A 2 GHz 130 mW Direct-Digital Frequency Synthesizer With a Nonlinear DAC in 55 nm CMOS
DC Field | Value | Language |
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dc.contributor.author | Yoo, Taegeun | - |
dc.contributor.author | Yeoh, Hong Chang | - |
dc.contributor.author | Jung, Yun-Hwan | - |
dc.contributor.author | Cho, Seong-Jin | - |
dc.contributor.author | Kim, Yong Sin | - |
dc.contributor.author | Kang, Sung-Mo | - |
dc.contributor.author | Baek, Kwang-Hyun | - |
dc.date.accessioned | 2021-09-05T02:39:59Z | - |
dc.date.available | 2021-09-05T02:39:59Z | - |
dc.date.created | 2021-06-15 | - |
dc.date.issued | 2014-12 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/96697 | - |
dc.description.abstract | This paper presents a direct digital frequency synthesizer (DDFS) based on the nonlinear DAC with a maximum operating frequency of 2 GHz. This work proposes three design methods to enhance the performance of a DDFS. First, a multi-level momentarily activated bias is proposed to reduce power dissipation in the phase accumulator. Second, a coarse phase-based consecutive fine amplitude grouping scheme is presented to reduce hardware complexity and power consumption in the digital decoder. Third, the mixed-wave conversion topology in the nonlinear DAC is proposed to improve the output spectral purity. The DDFS with 9 bit amplitude resolution is capable of producing a minimum spurious-free dynamic range (SFDR) of 55.1 dBc up to Nyquist frequency at the clock frequency of 2 GHz. The prototype DDFS is fabricated in a 55-nm CMOS. It occupies an active area of 0.1 mm(2) with a total power dissipation of 130 mW. The figure of merit of this DDFS is 8944 GHz . 2((SFDR/6))/W. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | PIPELINED PHASE ACCUMULATOR | - |
dc.subject | CLOCK FREQUENCY | - |
dc.subject | ARCHITECTURE | - |
dc.subject | DESIGN | - |
dc.subject | MHZ | - |
dc.title | A 2 GHz 130 mW Direct-Digital Frequency Synthesizer With a Nonlinear DAC in 55 nm CMOS | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Yong Sin | - |
dc.identifier.doi | 10.1109/JSSC.2014.2359674 | - |
dc.identifier.scopusid | 2-s2.0-84913603591 | - |
dc.identifier.wosid | 000345620100021 | - |
dc.identifier.bibliographicCitation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.49, no.12, pp.2976 - 2989 | - |
dc.relation.isPartOf | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.citation.title | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.citation.volume | 49 | - |
dc.citation.number | 12 | - |
dc.citation.startPage | 2976 | - |
dc.citation.endPage | 2989 | - |
dc.type.rims | ART | - |
dc.type.docType | Article; Proceedings Paper | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | PIPELINED PHASE ACCUMULATOR | - |
dc.subject.keywordPlus | CLOCK FREQUENCY | - |
dc.subject.keywordPlus | ARCHITECTURE | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordPlus | MHZ | - |
dc.subject.keywordAuthor | Direct digital frequency synthesizer (DDFS) | - |
dc.subject.keywordAuthor | digital-to-analog converter (DAC) | - |
dc.subject.keywordAuthor | segmented nonlinear DAC | - |
dc.subject.keywordAuthor | phase accumulator | - |
dc.subject.keywordAuthor | CMOS current mode logic | - |
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