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Compact Modeling for Circuit Simulation Considering TID Effect in 65nm CMOS Technology
Compact Modeling for Circuit Simulation Considering TID Effect in 65nm CMOS Technology
- 제목
- Compact Modeling for Circuit Simulation Considering TID Effect in 65nm CMOS Technology
- 제목 (타언어)
- Compact Modeling for Circuit Simulation Considering TID Effect in 65nm CMOS Technology
- 저자
- Lee, Hyung-Min
- 발행일
- 2019-07-01
- 학회명
- Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices
- 개최국가
- 대한민국
- 학회 개최일
- 2019-07-01 ~ 2019-07-03