반도체 공정에서의 Wafer Map Image 분석 방법론

Wafer Map Image Analysis Methods in Semiconductor Manufacturing System
  • 유영지; 
  • 안대웅; 
  • 박승환; 
  • 백준걸

초록

In the semiconductor manufacturing post-FAB process, predicting a package test result accurately in the wafer testing phase is a key element to ensure the competitiveness of companies. The prediction of package test can reduce unnecessary inspection time and expense. However, an analysing method is not sufficient to analyze data collected at wafer testing phase. Therefore, many companies have been using a summary information such as a mean, weighted sum and variance, and the summarized data reduces a prediction accuracy. In the paper, we propose an analysis method for Wafer Map Image collected at wafer testing process and conduct an experiment using real data.

키워드

Semiconductor; Wafer test; Package test; Wafer map image; Fail bit pattern
제목
반도체 공정에서의 Wafer Map Image 분석 방법론
제목 (타언어)
Wafer Map Image Analysis Methods in Semiconductor Manufacturing System
저자
유영지; 안대웅; 박승환; 백준걸
DOI
10.7232/JKIIE.2015.41.3.267
발행일
2015
저널명
대한산업공학회지
권
41
호
3
페이지
267 ~ 274