Intermediate Layer-Assisted Trap Density Reduction in Low-Power Optoelectronic Memristors for Multifunctional Systems

초록

The rapid expansion of the Internet of Things demands low-power devices that integrate memory, sensors, and logic functions. Perovskite materials show promise for low-power optoelectronic memristors; however, challenges such as nonuniform trap distribution and uncontrolled filament formation hinder their resistive switching performance. To overcome these issues, a TiO2 nanofilm via atomic layer deposition as a base layer for filament formation, is introduced. This layer passivates interfacial defects by forming strong chemical interactions with Pb2+ and I- ions at the perovskite interface, significantly reducing trap densities (interface trap density decreases 15-fold to 3.0 x 1016 cm-3, and bulk trap density to 1.8 x 1014 cm-3). Improved energy band alignment enables efficient electron transport, yielding a low-V SET (+0.24 V) and excellent low-power (approximate to 0.7 mu W) nonvolatile memory performance. Additionally, the device reliably detects near-infrared illumination as an optical input and enables reconfigurable image recognition using a 5 x 5 array under combined stimuli. It also facilitates the implementation of complex logic gates, such as AND, OR, and flip-flops. This paper demonstrates the potential for integrating nonvolatile memory, sensing, and logic functionalities into a single low-power device through the incorporation of a TiO2 nanolayer.

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