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A 7.7mW/1.0ns/1.35V Delay Locked Loop with Racing Mode and OA-DCC for DRAM interface
- 제목
- A 7.7mW/1.0ns/1.35V Delay Locked Loop with Racing Mode and OA-DCC for DRAM interface
- 저자
- KIM, Chulwoo
- 학회명
- IEEE International Symposium on Circuits and Systems
- 개최국가
- 프랑스
- 학회 개최일
- 2010-05-30 ~ 2010-06-02