Energy Efficient Hardware Architecture of LU Triangularization for MIMO Receiver

초록

An energy-efficient hardware architecture of complex-valued matrix lower-upper (LU) triangularization for multi-input-multi-output (MIMO) receivers is presented in this paper. In the LU triangularization process, Gaussian elimination operation is expressed as a series of vector-scalar products, where basic common computations can be precomputed and shared to reduce computational complexity. Our computation-sharing-based architecture was implemented using a 0.25-mu m CMOS process, and the hardware can perform LU triangularization from 2 X 2 to 8 X 8 matrices. Numerical results show that the proposed architecture has considerable energy savings over conventional matrix triangularization schemes.

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