Graphene arch gate SiO2 shell silicon nanowire core field effect transistors

  • Jin, J. E.
  • Lee, J. H.
  • Hwang, D. H.
  • Kim, D. W.
  • Kim, M. J.
  • 외 3명
Citations

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초록

We report the realization of graphene arch gate silicon nanowire field effect transistors with SiO2 shell serving as a gate insulator. The arch coverage of the SiO2 shell was achieved by the flexible graphene layers complying the top of the shell. The wrapping angle was defined by the relative strength of the van der Waals forces on the shell and the substrate. The leakage current of the graphene gate was only 55 fA, while the maximum on-off ratio of 16.7 was obtained. The effective mobility and quantum capacitance of the graphene layers were also obtained from the electronic transport data. (C) 2011 American Institute of Physics. [doi:10.1063/1.3663629]

키워드

THRESHOLD VOLTAGE
제목
Graphene arch gate SiO2 shell silicon nanowire core field effect transistors
저자
Jin, J. E.Lee, J. H.Hwang, D. H.Kim, D. W.Kim, M. J.Son, K. S.Whang, D.Hwang, S. W.
DOI
10.1063/1.3663629
발행일
2011-11-21
유형
Article
저널명
Applied Physics Letters
99
21