Engineering diffusion pathways in nanoporous epitaxial Si for CMOS-compatible Ni-silicide contacts with reduced resistance

초록

As Complementary Metal-Oxide-Semiconductor (CMOS) devices scale toward smaller nodes, contact resistance (RC) at the metal-silicon interface emerges as a critical performance bottleneck. Conventional silicides such as NiSi offer low resistivity but are limited by challenges in diffusion control and phase stability. In this study, we present a CMOS-compatible approach to reduce RC by tailoring Ni diffusion through a nanoporous epitaxial silicon (NP epi-Si) layer. NP epi-Si is a single-crystalline Si film with tunable nanoporosity, grown by lowtemperature plasma-enhanced chemical vapor deposition. The engineered porosity allows modulation of Ni diffusion during silicidation, enabling NiSi2 formation at just 450 degrees C, well below its typical formation temperature. The resulting NiSi2 exhibits a three-dimensional pyramidic geometry epitaxially aligned with the Si substrate. This structure increases the effective contact area and concentrates electric fields at the pyramid tips, lowering the Schottky barrier and enhancing carrier injection. Devices incorporating epitaxial NiSi2 achieve significantly lower RC than those with conventional NiSi contacts. All employed materials and processes are fully compatible with standard CMOS flows. This approach establishes NP epi-Si as a versatile platform for controlling silicide phase and interface properties, offering a practical, scalable pathway for RC reduction in next-generation semiconductor devices.

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