Analysis of a Multiwire, Multilevel, and Symbol Correlation Combination Scheme

  • Choi, Jonghyuck; 
  • Choi, Yoonjae; 
  • Park, Hyunsu; 
  • Sim, Jincheol; 
  • Kwon, Youngwook; 
  • ... Kim, Chulwoo; 
  • 외 1명
Citations

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6
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초록

The required data rate of wireline communications has increased; however, channel attenuation limits the data bandwidth. Bit-efficient signaling is an effective and efficient solution because more data can be transmitted at the same Nyquist frequency. Several methods for increasing bit efficiency, such as multi-wire signaling, multi-level signaling, and symbol correlation schemes, have been proposed. Each scheme can generate additional codes by encoding the data. Additional codes can be used to transmit more data or to embed data transitions. In this study, the aforementioned schemes are analyzed, and a method is developed to combine them, maximize the bit efficiency, and ensure the data transition density. For the prototype transceiver, a 4-wire PAM-3 (4W3P) signaling scheme was adopted. The 4W3P signaling scheme can increase the bit efficiency to 200% while maintaining the DC-balanced characteristics. Transceiver building blocks, such as the TX driver, feed-forward equalizer, and analog front-end, were optimized for the proposed signaling scheme. The prototype transceiver was fabricated using 28 nm CMOS technology, occupying 0.012 mm(2). The RX was measured using the TX and achieved a BER less than 10(-12) at 40 Gb/s over the four wires, with a total transceiver energy efficiency of 1.52 pJ/bit.

키워드

Bit-efficient signaling; clock-embedded signaling (CES); DC-balanced signaling; feed-forward equalizer (FFE); multi-level signaling; multi-wire signaling; pulse amplitude modulation (PAM); symbol correlation; transition density; TRANSCEIVER; CLOCK; PHASE
제목
Analysis of a Multiwire, Multilevel, and Symbol Correlation Combination Scheme
저자
Choi, Jonghyuck; Choi, Yoonjae; Park, Hyunsu; Sim, Jincheol; Kwon, Youngwook; Park, Seungwoo; Kim, Chulwoo
DOI
10.1109/TCSI.2022.3171796
발행일
2022-08
유형
Article
저널명
IEEE Transactions on Circuits and Systems I: Regular Papers
권
69
호
8
페이지
3416 ~ 3427